Senior SoC Network Subsystem Architect
Role details
Job location
Tech stack
Job description
The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems., Network Subsystem Architecture Definition
- Own end-to-end NSS architecture, including packet processing pipelines, protocol engines, and interface datapaths
- Architect high-performance packet pipelines supporting hundreds of millions of packets/sec throughput and processing flows
- Drive architectural direction for programmable vs. fixed-function pipeline balance and future extensibility
- Specify network subsystem pipeline scaling strategies and define multi-generation NSS architecture roadmap
- Lead design decisions for pipeline partitioning, feature scalability, and backward compatibility
QoS, Scheduling, and Flow Management
- Architect advanced scheduling frameworks (per-flow shaping, multi-level scheduling, traffic class isolation)
- Define QoS models to support multi-tenant workloads, virtualization, and service chaining
Debug, Telemetry, and Observability
- Define architecture for telemetry, performance counters, and real-time observability of pipeline behavior
- Architecture support for field debug, failure triage, and large-scale deployment monitoring
Cross-Functional Leadership
- Collaborate across SoC, compute, memory, SW/FW, validation, and customer teams to drive architecture closure
- Interface with external customers to translate workload requirements into NSS architecture decisions
- Lead architectural reviews and influence cross-team technical direction, This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Requirements
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates., Bachelor's degree in Electrical/Computer Engineering, Computer Science or related degree with 7 + years of experience.
You must have 7+ years of experience in the following:
- Networking ASIC / SoC / IPU / DPU architecture
- High-speed packet processing pipelines
- Experience in system-level architecture tradeoffs
- Define and deliver architecture for large-scale data center networking systems, * Experience with programmable datapath architectures (P4, pipeline microcode, or hybrid models)
- Experience with AI/HPC scale-out networking and congestion control architectures
- Transport protocols offloads
- QoS, scheduling, and multi-tenant isolation
- Familiarity with coherent or shared-memory offload models (e.g., CPU-IPU integration)
- Experience with hyperscaler deployments or customer co-design engagements
Benefits & conditions
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003) .
Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD