Senior DSP ASIC Architect - Optical Communication
Ciena
Brunswick, Germany
3 days ago
Role details
Contract type
Permanent contract Employment type
Full-time (> 32 hours) Working hours
Regular working hours Languages
English Experience level
SeniorJob location
Brunswick, Germany
Tech stack
Field-Programmable Gate Array (FPGA)
Python
System on a Chip
VHDL
Application Specific Integrated Circuits
Requirements
Do you have experience in Python?, Do you have a Doctoral degree?, * Knowledge of ASIC and FPGA design and system-on-chip integration using VHDL and related chip design flows
- Experience with photonic ICs and DSP co-design.
About the company
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact., Ciena enables next-generation high-speed connectivity through advanced optical communication innovation and a people-first culture. This role contributes to the architecture and development of coherent DSP solutions for 800G/1.6T transmission systems and beyond. The position plays a key role in advancing DSP ASIC technologies that power market-leading optical platforms., At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.