Senior Verification Engineer - Core Testbench & DV Methodology Lead

We are seeking a Senior or Principal Verification Engineer to assume ownership of our core (top-level) testbench, along with the verification methodology, tooling, and continuous integration infrastructure that support it. In this role, you will be responsible for evolving the top-level UVM environment, integrating unit-level verification IP, driving functional and code coverage closure across the core, and identifying verification gaps at the boundaries between units. You will also serve as a technical er within the organization, contributing to the company-wide initiative to advance AI-powered verification methodology. This position requires a rigorous, detail-oriented approach to verification and the ability to provide technical guidance and mentorship to engineers across the design verification organization., * Core testbench ownership - Own, improve, and continuously evolve the top-level core testbench and its UVM environment. Extend the testsuites, and integrate all the unit-level VIPs so block-level checkers, monitors, and coverage are reused at top level.

• Coverage - Own functional and code coverage at the core level: review the nightly results, drive closure across units, and audit covergroups and tests for real quality and intent.
• Cross-unit gap hunting - Find and close verification holes at the boundaries between units. Reconcile assume/guarantee relationships across unit testbenches: e.g., everything one module assumes about surrounding modules, needs to be verified by surrounding modules' testbenches.
• Methodology, tooling & CI - Own the verification flows (compile, coverage collection, regression) and the CI as the core RTL evolves: update compile configs, retire stale jobs, create new ones, keep regressions healthy and efficient. Drive concrete upgrades - migrate our scripts and flows to latest versions (e.g., start using Questa One and next-generation coverage, from Siemens, instead of the old flow) - and stay in regular contact with EDA vendors to keep us on the latest capabilities. Technical ership & mentorship - Act as the
• technical reference for core verification engineers, review block- and core-level testbench architectures, and mentor on coverage-driven and assertion-based verification.

Must Have

• 10+ years of hands-on design verification, including significant experience verifying processor cores (RISC-V ideally) or complex microarchitecture.
• Expert SystemVerilog and UVM; building reusable, configurable, multi-agent environments and integration testbenches.
• Strong functional-coverage and verification-planning skills.
• Deep hands-on Questa (our primary simulator) and a debug tool such as Visualizer / Verdi; other simulators (VCS, Xcelium) a plus.
• Strong Python scripting (plus Bash / Tcl) and practical ownership of verification CI/CD and regression infrastructure.
• Assertion-based verification (SVA) and the ability to reason about cross-block assume/guarantee contracts.
• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.

Nice to Have

• RISC-V Core Verification.
• Formal Verification.
• Emulation platforms (Veloce, ZeBu).
• Core/Bus interface protocols (e.g., AXI/CHI).

Essential Soft Skills

• An adversarial, gap-seeking mindset - instinctively asks "who actually checks this?" - with a strong umbrella view of the whole core.
• Clear communication across DV, design, and software teams; writes verification plans others can follow.

Why Seynamics?

• Work at one of Europe's most promising deep-tech semiconductor scale-ups.
• Accelerated development path.
• 4 days per week in the Barcelona office (city center), 1 WFH.
• 1 week of work from everywhere in the world.
• Competitive package.
• A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.