Technology Architect

implement, and verify advanced device architectures, including design examples and simulation models with comprehensive technical documentation. Collaborate with So C Architecture, verification, physical design, floorplan, and core teams to meet system performance, area, and power targets. Design coherent and non-coherent interconnects within the chip, including coherency protocol, directory structure, bandwidth, and latency targets. Evaluate new IPs, drive protocol deployments, and define system-wide guidelines for inter-operation of IPs in the So C. Deliver RTL to the So C team, support verification and silicon validation, and collaborate with software teams to ensure successful deployment of interconnects. Skills 7+ years of solid experience in IP/So C design. Working knowledge of System-on-Chip and Network-on-Chip architectures. General knowledge of on-chip network protocols: AMBA, AXI, CHI, ACE, APB. General knowledge of cache-coherent memory systems and interconnect. Familiarity

with RISC-V architecture. Proficiency with System Verilog or Verilog, C or C++, and scripting languages such as Python. Hands-on experience with So C design, Verilog RTL coding, and simulation software. General knowledge of functional and performance simulators. Good understanding of the design convergence cycle: architecture, micro-architecture, synthesis, timing closure, and verification. Soft Skills Team player focused on collective outcomes. Strong communication skills and ability to collaborate effectively with teammates. Positive, honest challenge mindset and willingness to have fun while striving for exceptional products. What We Offer Full-time position. Hybrid work environment with flexible schedule. Competitive remuneration commensurate with experience. Opportunities for personal and professional growth within an innovative team. Location Primary: Barcelona, SpainAlternative: Rome, Italy EEO Statement At Openchip & Software Technologies S. L., we believe a diverse and

About Openchip Openchip is a European Silicon Engineering Company headquartered in Barcelona, Spain. We aim to democratize the usage of chips by developing systems on chip (So Cs) that combine RISC-V and accelerated chiplets for AI and HPC, all interconnected with UCIe open interfaces. Our technologies serve AI, security, privacy, and carbon footprint reduction across fields such as high-performance computing, autonomous driving, telecommunications, personalized medicine, edge computing, and cloud. The Function The Network-on-chip Architecture team is multidisciplinary, involved from early product specification and analysis through to final RTL delivery of So Cs. We identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis, providing the So C team with design guidelines for bus protocol compliance and optimal power interconnect. Job Responsibilities Develop and verify state-of-the-art Memory Interface and Network-on-Chip IP cores. Define