Senior Embedded Software Engineer - Ethernet Retimers New

• Debug & System Integration
• Work directly with the system validation team to debug firmware behavior across different Ethernet configurations, link states, and failure modes
• Investigate and fix firmware issues in embedded C, leveraging deep understanding of how Layer 1 PHY, SERDES, FEC/PCS, MAC, and retimer components interact
• Serve as the connective tissue between firmware and system validation teams, triaging issues and driving them to resolution without long handoff loops
• Customer Bring-Up & Field Support
• Support customer bring-up and integration activities, including triaging field issues and coordinating fixes with internal teams
• Partner with field applications engineers to diagnose and resolve deployment issues quickly
• Firmware Feature Development
• Contribute to firmware feature development for SERDES configuration, link training, equalization, and diagnostics
• Partner with SoC, field applications, and platform teams across the full product lifecycle
• Help bring new Taurus products from initial silicon bringup through customer deployment

Do you have experience in SDKs?, * Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

• 5+ years of experience in firmware development or embedded systems engineering
• Hands-on experience with Ethernet at the system or device level: Layer 1 PHY, SERDES, retimers, gearboxes, NICs, switches, or related devices
• Solid embedded C/C++ skills and comfort working in a firmware codebase on real hardware
• Ability to debug across the hardware/software boundary: register accesses, embedded SDKs, link state machines, PHY telemetry, debug print logs
• Familiarity with Linux development tools: gcc/clang, make, bash, gdb, git
• Strong communication skills and comfort working in a fast-moving environment where the problem in front of you may not have a clean solution

Preferred Qualifications

• Experience with switch or NIC management software, SAI, or OpenBMC
• Knowledge of PMA, FEC, or other PHY-layer subsystems beyond the SERDES
• Background with retimer or gearbox firmware or SDK/API development
• Python scripting for debug, test automation, or data analysis
• Experience with lab equipment: BERT, oscilloscopes, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar
• Understanding of signal integrity: equalization, jitter, eye diagrams, link margin
• Prior experience mentoring engineers or leading debug efforts across teams

Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

5.05.0 out of 5 stars San Jose, CA $133,200 - $185,000 a year

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.