RTL Design Engineer

• Take responsibility for designing digital IP blocks from initial microarchitecture to RTL creation, integration, and supporting physical hardware development.
• Define and review module interfaces and system-level architecture.
• Actively leverage AI-based tools, agentic workflows, and automation frameworks to:
• Accelerate RTL design optimization and design-space exploration
• Assist in testbench generation and corner coverage
• Improve debug efficiency across simulation and silicon learning loops
• Define semicustom methodology for memory design
• Drive full-chip integration including CDC, Lint, synthesis, STA and power analysis.
• Collaborate with CAD, EDA, and software teams to integrate AI-driven flows into simulation, verification, and design sign-off environments.

Pay: $150,000.00 - $170,000.00 per year

Key Skills: LEC, QC, Lint, CDC, and Micro-Architecture