Senior Technical Lead - Post Silicon Validation

We are seeking a highly motivated and skilled Silicon Design Verification Engineer to join our fast-paced Hardware Engineering team in Sunnyvale, CA. In this role, you will play a critical part in ensuring the functional correctness of our next-generation, high-performance ASICs and SoCs. You will work closely with architecture and RTL design teams to develop comprehensive test plans, build scalable verification environments, and drive the verification process from concept to tape-out. If you are passionate about solving complex hardware challenges and pushing the boundaries of silicon performance, we want you on our team. Key Responsibilities Testbench Architecture: Design, develop, and maintain advanced, scalable verification environments and testbenches using SystemVerilog and UVM. Test Planning: Collaborate with RTL designers and hardware architects to define verification strategies and author comprehensive test plans for complex IP blocks and subsystems. Test Execution & Debug, 1. Provide Technical Guidance And Solutions By Defining, Advocating, And Implementing Best Practices In Post Silicon Validation Processes, Enhancing Team Capabilities And Productivity.

1. Conduct Comprehensive Code Reviews And Establish Quality Assurance Procedures While Optimizing Performance And Ensuring Adherence To Coding Standards For Successful Project Delivery.
2. Ensure Compliance With Processes In The Assigned Modules And Actively Participate In Technical Discussions, Serving As A Consultant For Feasibility Studies, Technical Alternatives, And Risk Assessments.
3. Collaborate With Stakeholders To Define Project Scope, Objectives, And Deliverables, And Prepare Status Reports To Mitigate Risks And Ensure Timely Project Completion.

Write directed and constrained-random tests. Triage and debug simulation failures, working directly with designers to root-cause and resolve RTL bugs. Coverage Closure: Define and analyze functional and code coverage metrics to ensure comprehensive verification of the design. Drive coverage closure to meet rigorous tape-out milestones. Flow & Tool Automation: Develop and maintain automation scripts (Python, Perl, Bash) to streamline simulation, regressions, and reporting flows. Verification Methodologies: Participate in the evaluation and adoption of new verification methodologies, formal verification techniques, and EDA tools. Gate-Level Simulation: Assist in running and debugging gate-level simulations (GLS) with and without timing constraints (SDF). * * * * * * * Minimum Qualifications * * * * * * * Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Experience: 3+ years of industry experience in ASIC/SoC pre-silicon verification. Hardware Languages: Strong proficiency in SystemVerilog and Verilog. Methodologies: Hands-on experience with UVM, OVM, or VMM methodologies. Problem Solving: Exceptional analytical and debugging skills with a proven track record of finding complex bugs in RTL designs. Scripting: Proficiency in at least one scripting language (Python, Perl, Makefile, or Bash). EDA Tools: Experience with industry-standard simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, or Siemens Questa). Preferred Qualifications * * * * * Advanced Degree: Master’s degree or Ph.D. in Electrical/Computer Engineering. Protocol Knowledge: Familiarity with standard interfaces and protocols (e.g., PCIe, CXL, DDR/LPDDR, Ethernet, AMBA AXI/AHB). Formal Verification: Experience using formal verification tools (e.g., JasperGold, VC Formal) to mathematically prove design properties. Emulation/FPGA: Experience with hardware emulation platforms (e.g., Palladium, Zebu) or FPGA prototyping. Power Aware Verification: Knowledge of UPF/CPF and experience with power-aware simulation techniques., 1. Strong Understanding Of Post Silicon Validation Techniques And Methodologies.

1. Excellent Proficiency In C And C++ Programming Languages For Validation Purposes.
2. Solid Knowledge Of Python Scripting For Automation And Tool Development.
3. Familiarity With Performance Optimization Techniques And Quality Assurance Practices In Semiconductor Testing., 1. Optional But Valuable Certifications: Certified Validation Engineer (Cve), Advanced Semiconductor Testing Certification (Astc).

3.73.7 out of 5 stars United States From $141,000 a year