Senior Technical Lead - Silicon Platform Validation, Python

1. Architect complex memory layout solutions using advanced design methodologies and tools such as Verilog, VHDL, and SystemVerilog, ensuring scalability, performance, and security.
2. Optimize memory allocation and data access patterns leveraging DRAM, SRAM, and cache technologies to enhance system throughput and efficiency.
3. Evaluate and integrate industry-leading memory management algorithms, applying expertise to address latency, fragmentation, and power consumption challenges.
4. Lead technical workshops and knowledge-sharing sessions within the team, promoting best practices and fostering proficiency in memory layout design.
5. Collaborate with stakeholders to gather requirements and translate business needs into high-performance architectural solutions using simulation and modeling platforms like Cadence and Synopsys.
6. Continuously research emerging memory layout technologies and trends, driving adoption of future-proof strategies that align with client and industry standards.
7. Define technology roadmaps and strategic initiatives for memory layout design, ensuring delivery of innovative solutions that mitigate risk and support business growth.

Do you have experience in Team development?, implementation of hardware and firmware changes at our manufacturing sites to ensure smooth transitions and minimal disruption. Documentation and Reporting: Track and document all active changes, open quality issues, and lessons learned to foster continuous improvement and knowledge sharing. Minimum Qualifications Bachelor’s degree in Electrical Engineering, Mechanical Engineering, or a related field. Proven experience in supplier/customer management. Demonstrated experience in creating supplier/customer quality reports. Strong analytical, problem-solving, and creative thinking skills with experience utilizing associated quality tools. Fluency in both English and Chinese is required. Must be able to work from manufacturing facilities daily. Ability to travel to other local manufacturing facilities as required., 1. Expert proficiency in memory layout design, demonstrating excellence in architecting and optimizing memory structures.

1. Advanced skills in hardware description languages such as Verilog, VHDL, and SystemVerilog for complex design implementations.
2. Strong understanding of memory hierarchy, including DRAM, SRAM, cache systems, and related management algorithms.
3. Advanced knowledge of simulation, modeling, and validation tools (e.g., Cadence, Synopsys) for architectural analysis and verification.
4. Excellent analytical and problem-solving abilities in addressing performance, latency, and security challenges.

5. Ability to lead technology strategy, mentor teams, and drive adoption of cutting-edge memory design practices. Other Requirements

6. Optional but valuable: Certified ASIC Design Professional (Cadence), Synopsys Certified Memory Design Expert.