Principal Firmware/Middleware Engineer

Experteer Overview As Principal Firmware Architect for UALink Switch, you define and drive the end-to-end embedded software and firmware architecture for next-generation AI cluster scale-up switches. You bridge silicon and orchestration software, shaping how firmware utilizes hardware to maximize bandwidth, minimize latency, and ensure reliability across thousands of accelerators. You lead firmware design across initialization, topology, and platform orchestration exposed to BMCs via OpenBMC and Redfish. This role offers impact in a cutting-edge, server-scale domain with significant cross-functional collaboration. Compensation / Benefits * Architect and specify the low-level firmware for the UALink Switch ASIC * Collaborate with ASIC design, RTL, and verification teams to define interfaces, registers, and memory maps * Define firmware stack for UALink physical, link, and transport layers including flow control and routing * Design deterministic link-training state machines for ultra-high-speed connections * Develop topology discovery, dynamic routing, and credit management to prevent fabric congestion * Lead SDKs and APIs exposing switch functionality to BMCs via OpenBMC and Redfish * Fine-tune bare-metal execution for deterministic low latency on collective communication primitives * Design robust RTOS-agnostic RAS micro-architectures and secure boot / attestation mechanisms Tasks * 15+ years in embedded systems, server platform architecture, or low-level silicon firmware * Expert in C for bare-metal and RTOS (ThreadX, FreeRTOS, Zephyr) * Python proficiency for hardware automation and modeling * Deep knowledge of high-speed interconnect protocols (UALink, NVLink, CXL, PCIe Gen5/6) * Strong understanding of credit-based flow control, packet routing, PHY equalization, SerDes management * Experience with hardware debuggers (JTAG, Lauterbach TRACE32) and lab equipment (Oscilloscopes, PCIe Protocol Analyzers) Key requirements * competitive benefits package

Engineer connections * Develop topology discovery, dynamic routing, and credit management to prevent fabric congestion * Lead SDKs and APIs exposing switch functionality to BMCs via OpenBMC and Redfish * Fine-tune bare-metal execution for deterministic low latency on collective communication primitives * Design robust RTOS-agnostic RAS micro-architectures and secure boot / attestation mechanisms Tasks * 15+ years in embedded systems, server platform architecture, or low-level silicon firmware * Expert in C for bare-metal and RTOS (ThreadX, FreeRTOS, Zephyr) * Python proficiency for hardware automation and modeling * Deep knowledge of high-speed interconnect protocols (UALink, NVLink, CXL, PCIe Gen5/6) * Strong understanding of credit-based flow control, packet routing, PHY equalization, SerDes management * Experience with hardware debuggers (JTAG, Lauterbach TRACE32) and lab equipment (Oscilloscopes, PCIe Protocol Analyzers) Key requirements * competitive benefits package