Principal Firmware/Middleware Engineer

Experteer Overview As Principal Firmware Architect, you define and drive the end-to-end embedded firmware architecture for next-generation AI cluster switch solutions. You bridge ASIC design and higher-level cluster software to maximize bandwidth, minimize latency, and ensure reliability across thousands of accelerators. You shape the firmware stack, initialization and management, and performance/RAS/security capabilities. This role offers impact across hardware-software co-design and platform orchestration with cross-functional teams. Compensation / Benefits * Architect and specify firmware for the UALink Switch ASIC microcontrollers * Collaborate with ASIC, RTL, and verification teams to define interfaces and memory maps * Define firmware stack for UALink physical, link, and transport layers * Design fast link-training state machines for high-speed connections * Develop topology discovery, routing, and credit management for fabric efficiency * Lead SDKs/APIs exposing switch functionality to BMCs via OpenBMC and Redfish * Tune latency and bandwidth for deterministic collective operations * Design RAS architectures including telemetry, fault isolation, and security features Tasks * 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware * Expert-level C for bare-metal/RTOS and Python for hardware automation * Deep understanding of high-speed interconnect protocols (UALink, NVLink, CXL, PCIe Gen5/Gen6) * Knowledge of credit-based flow control, routing, and SerDes management * Experience with hardware debuggers (JTAG, Lauterbach TRACE32) and lab equipment Key requirements * competitive benefits package

stack to BMCs via OpenBMC and Redfish * Tune latency and bandwidth for deterministic collective operations * Design RAS architectures including telemetry, fault isolation, and security features Tasks * 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware * Expert-level C for bare-metal/RTOS and Python for hardware automation * Deep understanding of high-speed interconnect protocols (UALink, NVLink, CXL, PCIe Gen5/Gen6) * Knowledge of credit-based flow control, routing, and SerDes management * Experience with hardware debuggers (JTAG, Lauterbach TRACE32) and lab equipment Key requirements * competitive benefits package