Design Engineer III

Everforth Apex
Sunnyvale, CA, United States
6 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Compensation
$145,600.0 - $166,400.0
Working hours
Regular working hours
Job source

Tech stack

Data Analysis Computer Engineering Software Debugging Logic Synthesis of Circuits Perl (Programming Language) Formal Verification Python (Programming Language) Machine Learning SystemVerilog Information Technology

Job description

This position is for a Design Verification engineer focused on wearables silicon accelerator IPs. The role involves testbench development, coverage-driven verification, RTL debug, and power and performance measurement. The successful candidate will work with a small team to build and run testbenches, analyze coverage, debug failures, and measure power and performance., * Develop and execute verification plans for RTL blocks and IPs across the subsystem.

  • Build and maintain SystemVerilog/UVM testbenches, and write directed and constrained-random tests.
  • Drive functional coverage and assertion (SVA) closure, and run and triage regressions.
  • Perform power and performance measurement across design stages using specified tools and correlate results with post-silicon data.
  • Build a power and performance dashboard for tracking and publishing results.
  • Debug RTL failures using waveform tools and provide feedback to the design and verification teams.
  • Contribute to the automation of verification, regression, and power/performance measurement flows using Python.

Requirements

Education: A Bachelor of Science in Electrical/Computer Engineering or Computer Science is required., * Proven SystemVerilog and UVM verification experience, including testbench architecture, sequences, and drivers/monitors.

  • Experience with functional coverage, constrained-random, and assertion-based verification (SVA) and coverage closure.
  • Strong RTL debug skills with industry simulators (VCS, Xcelium, or Questa) and waveform tools like Verdi.
  • Working knowledge of RTL design principles and digital design fundamentals.
  • Proficiency in Python or Perl scripting for automation., * An MS in a relevant field is preferred.
  • Experience with power measurement tools such as PrimeTime PX (PTPX) or equivalent.
  • Experience with low-power or power-aware verification (UPF, power-aware simulation) in advanced nodes (7nm and below).
  • Formal verification or emulation (Palladium / Zebu) experience.
  • Familiarity with the RTL-to-GDSII flow.
  • Experience with data analysis or machine learning approaches for coverage or debug triage.

About the company

Everforth Apex is a world-class IT services company that serves thousands of clients across the globe. When you join Everforth Apex, you become part of a team that values innovation, collaboration, and continuous learning. We offer quality career resources, training, certifications, development opportunities, and a comprehensive benefits package. Our commitment to excellence is reflected in many awards, including ClearlyRateds Best of Staffing in Talent Satisfaction in the United States and Great Place to Work in the United Kingdom and Mexico.

Everforth Apex uses a virtual recruiter as part of the application process. Click for more details. By applying for this job, you agree to receive calls, AI-generated calls, text messages, or emails from Everforth Apex and its affiliates, and contracted partners. Frequency varies for text messages. Message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You can reply STOP to cancel and HELP for help. You can access our privacy policy at

Apply for this position

This job is hosted externally. Click below to view the full posting and apply.

Apply on www.dice.com

Good distractions

Talks and stories from around this role — technically off-topic, practically not.

2:36 min

Applying supervised machine learning for practical rule extraction

Katja Träumner

1:48 min

Automating exploratory data analysis within training pipelines

Dora Petrella · WWC 2023

1:20 min

Identifying multi-disciplinary talent for developer experience engineering roles

Hazal Mestci +1 · Coffee With Developers

1:57 min

Evolution of machine learning algorithms and computing hardware

Alexandra Waldherr · LIVE

1:36 min

Performing exploratory data analysis to uncover underlying patterns

Julian Joseph · LIVE

59 sec

State of the art in software verification

Onur Kasimlar Onur Kasimlar · WWC 2025

Videos

See all

Related articles

See all