Sr Datacenter GPU Lead Power Constrained Performance Architect

Advanced Micro Devices, Inc.
Austin, TX, United States
6 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Compensation
$178,400.0
Working hours
Regular working hours

Tech stack

Computer-Aided Design Artificial Intelligence Boolean Algebra Computer Engineering Data Centers Software Debugging Rollup Large Language Models Information Technology Power Analysis (Cryptography) Physical Design

Job description

  • Own power-constrained performance modeling, projections, implementation target setting and attainment tracking from Concept-exit (pre-si) to Product launch (post-si) for AMD Instinct AI/ML/HPC accelerators
  • Work with business unit and product architecture to define product configurations, capabilities and P&P targets
  • Cross functionally lead P&P attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Power Management, Post-si validation
  • Roll-up Power/Performance readouts, present in executive forums, motivate cross-functional teams on power efficiency improvements
  • Mentor junior engineers and develop skillsets and methodologies in the team for important PPA domains like Power Modeling at various stages of SoC development, Cdyn/Leakage/STA/Area trade-offs and attainment, Silicon Power/Performance debug, Post Si calibration of models, Work-load power analysis, AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

Requirements

  • Background in Computer Architecture, Processor/Accelerator development
  • Experience in Power/Performance projections, modeling and optimization at SoC or System level
  • Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc..)
  • Familiarity with post-silicon power/performance debug, model correlation
  • Fluency in communicating with various engineering teams, business leads and executive management
  • Knowledge of DL/ML/LLM/MoE workloads will be a bonus EDUCATION:

  • Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or related

About the company

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward.

AMD’s Datacenter Performance Group is seeking a senior Power & Performance Architect for driving the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve owning the Perf@Power attainment of a leading generation of our Instinct accelerators, providing cross-functional leadership for a virtual team that drives all aspects of Perf@Power attainment, including pre-Si modeling, post-Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll-ups and reporting, methodology innovations and development. Being passionate about performance and power efficiency, influence without authority and excellent communication skills are key ingredients for success in this role.

Apply for this position

This job is hosted externally. Click below to view the full posting and apply.

Apply on diversityjobs.com

Good distractions

Talks and stories from around this role — technically off-topic, practically not.

3:22 min

Solving equation combinations with constraint loops

Balkrishna Rawool Balkrishna Rawool · WWC 2024

51 sec

Repurposing hardware and operating underwater data centers

Chris Heilmann +1 · LIVE

4:33 min

Handling complete production optimizations with modern build tools

JS Congress

1:12 min

Addressing the competitive landscape of specialized hardware demands

Hazal Mestci +1 · Coffee With Developers

4:08 min

Minimizing data center power loss through efficient hardware design

Alexander Gerfer Alexander Gerfer +3 · WWC Europe 2026

4:03 min

Managing massive power consumption scaling in AI data centers

Stephan Gillich Stephan Gillich +3 · WWC 2024

Videos

See all

Related articles

See all