ASIC/SOC DFT Engineer (Silicon Engineering)

Experteer Overview In this role you will develop and verify next-generation ASICs for space and ground infrastructure, contributing to Starlink’s global connectivity. You will collaborate with cross-disciplinary teams to implement and validate DFT features, scan insertion, and test content for high-reliability silicon. Your work will help expand performance and reliability of SpaceX systems used worldwide. This opportunity offers hands-on design and verification work at the cutting edge of space-grade silicon engineering. Compensation / Benefits * Evaluate design readiness for scan insertion through RTL and physical design * Use scan DRC tools and validate DFT fabrics and IP within subsystems * Run and optimize scan insertion via synthesis tools for maximum coverage * Perform ATPG analysis to ensure quality scan chain construction and coverage goals * Run non-timing and SDF annotated gate-level simulations and debug * Create ATPG content for post-silicon testing and validate via gate-level simulations * Collaborate with circuit physical design, ATPG, and manufacturing teams to ensure high-quality silicon scan coverage Tasks * Bachelor’s degree in electrical engineering, computer engineering, or computer science * 1+ years of professional experience with ASICs * Experience in scan insertion or DFT setup Key requirements *

ATPG, simulations * Collaborate with circuit physical design, ATPG, and manufacturing teams to ensure high-quality silicon scan coverage Tasks * Bachelor’s degree in electrical engineering, computer engineering, or computer science * 1+ years of professional experience with ASICs * Experience in scan insertion or DFT setup Key requirements *