Principal FPGA Digital Engineer - 3

Northrop Grumman
Chandler, AZ, United States
4 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours

Tech stack

Configuration Management Computer Engineering Software Debugging Ethernet Firmware Field-Programmable Gate Array (FPGA) Hardware Description Language Hardware Design PCI Express Systems Development Life Cycle Static Timing Analysis System on a Chip
+6 more
Universal Asynchronous Receiver/Transmitter Verilog VHSIC Hardware Description Language (VHDL) Vivado ModelSim Hardware Testing

Job description

Experteer Overview In this role you drive FPGA design and validation for Space Systems, partnering with cross-functional teams to ensure reliable hardware integration. You develop advanced test benches and contribute to image processing and IO HDL modules, while upholding design standards. You work in a fast-paced, collaborative environment and help shape high-assurance electronic systems for aerospace applications. Join a mission-driven team that pushes the boundaries of space technology to deliver impact. Compensation / Benefits * Collaborate with senior FPGA engineers and multidisciplinary teams to address design and integration challenges * Develop and execute advanced test benches to verify functional and timing requirements of FPGA designs * Generate, verify & integrate IO and image processing HDL modules with device architecture * Ensure compliance with internal design standards throughout the development lifecycle * Oversee configuration management of multiple FPGA bitstream build configurations for varied use cases * Prepare, present, and maintain comprehensive design documentation (schematics, simulations, verification reports) * Continuously expand technical knowledge of evolving FPGA technologies, tools, and methodologies Tasks * Bachelor in Electrical Engineering, Computer Engineering, or related discipline with 5 years of relevant experience; or Master with 3 years; or PhD with 1 year * Ability to obtain U.S. DoD Secret security clearance at time of application * Solid FPGA/SoC design background with complex firmware development using VHDL (preferred) or Verilog * Significant experience with AMD Xilinx FPGAs and SoCs * Knowledge of timing, power, I/O constraints and static timing analysis using Vivado IDE * Proficiency in MOSA interfaces/buses (Ethernet, PCIe, AXI4, UART, SDLC) and debugging tools * Experience with simulation tools (Questa/ModelSim) and hardware debuggers (logic analyzers, oscilloscopes) * Experience creating verification plans using simulation, analysis, and hardware bench testing * Understanding OSVVM or UVM (OSVVM preferred) Key requirements * health insurance * life and disability insurance * savings plan * Company paid holidays * paid time off (PTO) * bonus eligibility

Requirements

build configurations for varied use cases * Prepare, present, and maintain comprehensive design documentation (schematics, simulations, verification reports) * Continuously expand technical knowledge of evolving FPGA technologies, tools, and methodologies Tasks * Bachelor in Electrical Engineering, Computer Engineering, or related discipline with 5 years of relevant experience; or Master with 3 years; or PhD with 1 year * Ability to obtain U.S. DoD Secret security clearance at time of application * Solid FPGA/SoC design background with complex firmware development using VHDL (preferred) or Verilog * Significant experience with AMD Xilinx FPGAs and SoCs * Knowledge of timing, power, I/O constraints and static timing analysis using Vivado IDE * Proficiency in MOSA interfaces/buses (Ethernet, PCIe, AXI4, UART, SDLC) and debugging tools * Experience with simulation tools (Questa/ModelSim) and hardware debuggers (logic analyzers, oscilloscopes) * Experience creating verification plans using simulation, analysis, and hardware bench testing * Understanding OSVVM or UVM (OSVVM preferred) Key requirements * health insurance * life and disability insurance * savings plan * Company paid holidays * paid time off (PTO) * bonus eligibility

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