BIOS Engineer

Monolithic Power Systems
San Jose, CA, United States
1 day ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
3 years minimum
Compensation
$140,000.0 - $220,000.0
Working hours
Regular working hours
Languages
American Sign Language

Tech stack

Board Bringup C (Programming Language) Microsoft Windows Advanced Configuration and Power Interface (ACPI) Adobe InDesign Systems Engineering Intelligent Platform Management Interface Bash Shell BIOS C++ (Programming Language) Configuration Management Computer Engineering
+29 more
Continuous Delivery Continuous Integration Datasheets Software Debugging Device Drivers Microprocessors Dynamic Random-Access Memory Firmware Hardware Design Interoperability Joint Test Action (IEEE Standards) Python (Programming Language) PCI Express Reduced Instruction Set Computing Serial Communications Subsystems Systems Architecture System Programming System Testing Universal Asynchronous Receiver/Transmitter USB Scripting Extensible Firmware Interface Git Information Technology U-Boot Multiplatform Software Version Control Hardware Debugging

Job description

We are seeking a skilled and motivated Senior BIOS Engineer to join our system engineering team. In this role, you will work closely with Systems Engineers to troubleshoot, validate, and optimize firmware and low-level software across a diverse portfolio of platforms built on AMD, Intel, and ARM-based CPUs, with a focus on DDR memory subsystems and other critical components. You will play a key role in bringing up/troubleshooting and validating memory subsystem/components on different platforms, resolving complex hardware-software interface issues, and ensuring robust interoperability/compatibility of subsystems/components and production readiness. Key Responsibilities

  • Analyze, troubleshoot, and customize BIOS/UEFI firmware for platforms using AMD EPYC/Ryzen, Intel Core/Xeon, and ARM-based processors.
  • Collaborate closely with Systems Engineers to troubleshoot and validate subsystems and components across the full platform stack.
  • Lead BIOS-level bring-up and validation for new hardware platforms, including debug of CPU, chipset, and memory (DDR5) subsystems.
  • Analyze and resolve hardware-firmware interface issues including POST failures, memory training errors, PCIe enumeration problems, and thermal/power sequencing anomalies.
  • Configure and validate DDR5 memory subsystems, including SPD/XMP programming, memory training tuning, RAS features, and JEDEC compliance.
  • Develop and execute validation test plans for BIOS features, power management (ACPI/S-states), security features (Secure Boot, TPM, AMD PSP, Intel TXT/SGX), and boot flows.
  • Work with CPU vendors to ensure the adoption of certain BIOS customization for certain platforms
  • Debug using industry-standard tools such as JTAG/ITP debuggers, logic analyzers, oscilloscopes, and serial console output.
  • Author and maintain issue logs/notes, validation reports, debug guides, and internal technical documentation.
  • Participate in design reviews, hardware bring-up planning, and cross-functional meetings
  • Support manufacturing and sustaining engineering with BIOS customization, factory programming, and field issue resolution.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.
  • 3+ years of hands-on experience in BIOS/UEFI firmware development or validation.
  • Strong understanding of DDR5 memory architecture, training algorithms, SPD/MR registers, and RAS features is highly desired.
  • Demonstrated experience with at least two of the following CPU architectures: AMD (AGESA, EPYC/Ryzen), Intel (FSP, Core/Xeon), or ARM (TF-A, EDK2).
  • Proficiency in C/C++ and scripting languages (Python, Bash) for firmware development and automation.
  • Experience with UEFI/EDK2 framework, SMM, DXE, PEI driver development, and ACPI/ASL.
  • Familiarity with hardware debug tools: JTAG debuggers (Intel ITP, Lauterbach), protocol analyzers, oscilloscopes, and serial console interfaces.
  • Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.
  • Experience reading and interpreting hardware schematics, datasheets, and silicon vendor documentation.
  • Excellent analytical and problem-solving skills with the ability to work across hardware and software boundaries.
  • Strong written and verbal communication skills; experience authoring technical documentation., * Experience with AMD PSP, Intel ME/CSME, or ARM TrustZone security subsystems.
  • Familiarity with BMC firmware (OpenBMC) and IPMI/Redfish management interfaces.
  • Knowledge of server platform RAS features: DRAM ECC, memory mirroring, patrol scrub, and machine check architecture (MCA).
  • Exposure to PCIe Gen 5 or CXL 2.0/3.0 interconnect validation.
  • Hands-on experience with JEDEC DDR5 compliance testing and memory timing optimization.
  • Understanding of power management frameworks: ACPI, AMD STAPM, Intel DPTF, and platform telemetry.
  • Prior collaboration with silicon vendors (AMD, Intel, Arm Ltd.) on pre-silicon or early-silicon bring-up.
  • Experience with version control systems (Git), CI/CD pipelines, and agile engineering workflows.
  • Proficiency with Windows debugging environments for BIOS/firmware development., ARM (Advanced RISC Machine), Algorithms, Analysis Skills, Automation, Bash Scripting, Boundary Scan, C Programming Language, C++ Programming Language, CPU (Central Processing Unit), Chipset, Communication Skills, Computer Engineering, Computer Firmware, Computer Science, Continuous Deployment/Delivery, Continuous Integration, Cross-Functional, DRAM, Datasheets, Debugging Skills, Debugging Tools, Device Drivers, Diversity, Documentation, Electrical Engineering, Genetics, Git, Hardware Administration, Hardware Debugging, Hardware Design, I2C, IPMI (Intelligent Platform Management Interface), Identify Issues, Industry Standards, Instrumentation, Intel Product Family, Interoperability, Joint Electron Device Engineering Council (JEDEC), Logic Analyzer, Manufacturing, Memory Hardware, Memory Subsystem, Memory Testing, Microsoft Windows Operating System, Multiplatform/Cross-Platform, Oscilloscope, PCI Express (PCI-E), Power Management, Presentation/Verbal Skills, Problem Solving Skills, Protocol Analysis, Python Programming/Scripting Language, Schematics, Scripting (Scripting Languages), Semiconductors, Serial Link Design, Silicon Bringup, Source Code/Configuration Management (SCM), Sustainability, System Architecture, System Validation, Systems Engineering, Team Player, Technical Writing, Telemetry, Testing, USB, Universal Asynchronous Receiver-Transmitter (UART), Validation Plan, Validation Testing, Willing to Travel, Writing Skills

Benefits & conditions

This role requires close day-to-day collaboration with Systems Engineers, Hardware Engineers, and Design/Applications Engineers in a fast-paced lab environment. You will have access to pre-production hardware, silicon support, and a dedicated debug lab equipped with industry-standard instrumentation. Occasional travel to vendor or customer sites may be required. What We Offer

  • Competitive salary and equity compensation.
  • Comprehensive health, dental, and vision benefits.
  • Opportunity to work on cutting-edge hardware with next-generation silicon.
  • Collaborative, technically rigorous team culture.
  • Flexible work arrangements and professional development support.

MPS offers a comprehensive benefits package. We provide health care coverage, dental and vision, 401(K) with a company match, Employee Stock Purchase Program (ESPP), up to 11 company paid holidays, and 15- 20 days of paid time off depending on your tenure, generous discretionary company bonuses, and life and disability protection. Employees in sales positions may be eligible for our sales incentive bonuses. Employees in certain positions may be eligible for stock compensation. For more information on MPS’ benefits please view our company website at www.monolithicpower.com.

Pay is based on market location and may vary based on factors including experience, skills, education and other job-related reasons. The base salary range for this position in California is $140,000 - $220,000.

About the company

Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world —come join our team and see how YOU can make a difference.

Apply for this position

This job is hosted externally. Click below to view the full posting and apply.

Apply on www.careerbuilder.com

Good distractions

Talks and stories from around this role — technically off-topic, practically not.

41 sec

Massive client data loss and bio-digital storage

Chris Heilmann +1 · LIVE

5:35 min

Direct hardware communication using the Web USB API

Rowdy Rabouw Rowdy Rabouw · WWC 2025

6:21 min

Investigating push inefficiencies with upstream Git experts

Jonathan Creamer · Coffee With Developers

2:34 min

Selecting specific microcontrollers and fundamental programming languages for powertrains

David Romić · WWC 2023

2:55 min

Bidirectional hardware communication using the web USB API

George Cave · WWC 2023

3:20 min

Certifying safety-critical automotive software and deploying progressive testing strategies

David Romić · WWC 2023

Videos

See all

Related articles

See all