STA Engineer

Intellectual Capital Resources Limited
Cambridge, UK
about 2 months ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Job source

Tech stack

Artificial Intelligence Data Analysis Data Centers Software Debugging Electronic Design Automation Perl (Programming Language) Python (Programming Language) Signal Integrity Static Timing Analysis Tcl (Programming Language) Scripting Application Specific Integrated Circuits
+1 more
Physical Design

Job description

I am currently working with an established technology company in Cambridge that develops a range of high-volume computing and embedded products. Due to continued growth, they are looking to hire a STA Engineer to join its expanding team. This is an excellent opportunity for a STA Engineer to work within a highly collaborative team, contributing across the full chip development lifecycle from early design stages through to silicon delivery and product release. The team is relatively small, giving engineers broad exposure and the opportunity to have a genuine impact on product development. The successful STA Engineer will have experience in: Performing full-chip and block-level static timing analysis on complex ASIC and SoC designs Driving timing closure across all implementation stages, from synthesis through to sign-off Analysing and resolving setup, hold, clock gating and signal integrity issues Developing timing constraints and ensuring accurate timing models and methodologies are implemented Working closely with Physical Design, RTL Design and Verification teams to optimise performance, power and area (PPA) Supporting sign-off activities including STA, timing verification and silicon bring-up readiness Debugging and resolving complex timing issues within advanced process nodes

Requirements

A strong academic background in Electronics, Electrical Engineering or a related discipline Proven industry experience in Static Timing Analysis, Physical Design or ASIC implementation Deep understanding of timing closure methodologies and sign-off flows for advanced ASIC and SoC designs Strong knowledge of industry-standard EDA tools such as Synopsys PrimeTime, Design Compiler and place-and-route tools Experience working on complex, high-performance semiconductor products, ideally within AI, HPC or data centre applications Strong scripting skills using Tcl, Perl or Python to automate timing analysis and improve design methodologies Excellent communication skills and the ability to work effectively within cross-functional engineering teams This is a fantastic opportunity to join a company with a strong engineering culture, work on technically challenging products and become part of a close-knit team where your contributions will have a direct impact.

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