STA Engineer

reports and drive closure actions * Contribute to timing methodology improvements * Support tape out readiness from a timing perspective Requirements: * Senior level experience in static timing analysis * Strong experience with top level timing constraints * Strong knowledge of SDC and timing exceptions * Experience with clock and reset strategy * Experience supporting timing closure for SoC or complex ASIC designs * Familiarity with physical implementation flows * Strong scripting skills, Tcl, Python or Shell * Experience with EDA timing tools * English level C1 * Bachelor, Master or PhD in Electrical Engineering, Microelectronics, Computer Engineering or related field Preferred / Valued knowledge: * Experience working with RISC V architecture is highly valued, especially within processor, SoC, RTL, verification, firmware, software, PCIe, DDR, PCS, DFT, Physical Design or hardware environments. What’s in it for you? Our client offers an exciting, challenging role in a

collaborative, dynamic environment. The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future. Benefits: - Flexible working hours (office open between 7 AM and 9 PM, employees manage their own schedule) - Hybrid working model - One week per year work from anywhere - 25 days annual leave plus December 24 and 31 - €150 per month food allowance ( €1800 per year additional compensation) - Private medical insurance - One time relocation bonus paid with the first salary - Support with housing search through an agency - Visa support if required - Relocation support for family - Virtual shares - Language classes (Spanish, English, Catalan) - Tax incentive