Senior Staff Performance Codesign Engineer, TPU

Experteer Overview In this role you will define and drive the technical roadmap and architecture for AI hardware-software systems, enabling high-performance training and inference for large ML models. You will bridge research, software, and hardware teams to push model architecture and accelerator innovations at scale. You will architect next-gen simulation frameworks and performance models to rigorously evaluate micro-architectural decisions. You contribute to shaping Google’s TPU strategy and production-ready, power-efficient accelerators in a hyperscale environment. Compensation / Benefits * Define and drive the technical roadmap and architecture for hardware/software stack * Serve as technical liaison between research, software, and hardware teams to steer model architecture innovations * Architect and oversee development of configurable simulation frameworks and cycle-accurate performance models * Advocate system-level performance analysis across distributed ML systems and balance compute, memory bandwidth, and inter-chip networks * Manage cross-functional partnerships across hardware engineering, compiler development, and ML research to influence strategy and production transition * Contribute to TPU architecture, verification, and integration within AI/ML-driven systems * Shape long-term architectural roadmap for future ML training and serving capabilities * Promote integration of foundational ML research with custom silicon for high performance and efficiency * Support Google Cloud and global users by delivering scalable AI hardware technologies Tasks * Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; equivalent practical experience * 12 years of experience in computer architecture, chip architecture, or hardware-software co-design * Experience developing systems for performance modeling, simulation, or system analysis Key requirements * bonus target * equity * benefits

compute, memory bandwidth, and inter-chip networks * Manage cross-functional partnerships across hardware engineering, compiler development, and ML research to influence strategy and production transition * Contribute to TPU architecture, verification, and integration within AI/ML-driven systems * Shape long-term architectural roadmap for future ML training and serving capabilities * Promote integration of foundational ML research with custom silicon for high performance and efficiency * Support Google Cloud and global users by delivering scalable AI hardware technologies Tasks * Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; equivalent practical experience * 12 years of experience in computer architecture, chip architecture, or hardware-software co-design * Experience developing systems for performance modeling, simulation, or system analysis Key requirements * bonus target * equity * benefits