Digital Design Engineer iv)

Infineon
Villach, Austria
6 days ago
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Role details

Contract type
Internship / Graduate position
Employment type
Full-time (> 32 hours)
Experience level
Starter
Experience required
0 years minimum
Compensation
€62,610.0
Working hours
Regular working hours
Languages
English, German

Tech stack

Boolean Algebra Computer Engineering Software Debugging Digital Electronics Logic Synthesis of Circuits SystemVerilog VHSIC Hardware Description Language (VHDL) Physical Design

Job description

  • Support microarchitecture design and specification activities based on system-level requirements
  • Contribute to the development of scalable and reusable digital IPs to meet platform and project requirements
  • Collaborate with cross-functional teams, including system architects, software engineers, and validation teams, to support seamless product integration
  • Work with analog design teams on interface protocols and mixed-signal partitioning
  • Perform RTL design and implementation of digital logic for infrastructure IPs in the area of POWER, CLOCK, RESET, SAFETY and CONTROL
  • Assist with power intent design using UPF, Clock/Reset domain crossing (CDC/RDC) analysis, and DFT/ATPG integration
  • Participate in synthesis, power/performance/area (PPA) optimization, and work closely with the physical design team to help achieve design closure
  • Support verification teams in block-level and system-level verification activities, helping to debug and resolve identified issues
  • Help ensure designs meet automotive safety standards by implementing required safety mechanisms
  • Identify and help resolve technical issues related to design, timing, and functionality with support from senior team members

Requirements

  • Master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • 0-2 years of professional experience in digital design - Fresh graduates with strong academic projects are encouraged to apply
  • Experience with internships or academic projects involving digital design or verification is a strong plus
  • Knowledge of RTL coding using SystemVerilog or VHDL
  • Experience with debugging digital circuits
  • Strong problem-solving skills and ability to work independently as well as in a team
  • Excellent communication skills for cross-functional collaboration
  • Proficiency in English, German is a plus

About the company

We are filling this position through one of our leasing partners. A valid work permit for Austria (RWR+ Card) or EU citizenship is a prerequisite for this position. This position is subject to the collective agreement for workers and employees of EEI with a minimum salary of € 4.472,11 (https://www.feei.at/wp-content/uploads/2024/04/minimum-salaries-white-collar-workers-2025.pdf). The monthly salary is paid 14 times p.a. A higher payment is negotiable depending on your expertise and skills.

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