ASIC Engineer - Early Career

• Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs
• Support module-level and subsystem-level verification using SystemVerilog/UVM
• Write test plans and functional coverage definitions under guidance from senior team members
• Assist with CDC/RDC/LINT checks and clean-up
• Participate in code coverage and functional coverage closure activities
• Help develop assertions, protocol monitors, and scoreboards for testbenches
• Support integration and verification of external IP (e.g., bus fabrics, standard interfaces)
• Learn and apply industry-standard verification methodologies (UVM, formal verification basics)
• Debug RTL and testbench issues with guidance from senior engineers
• Document design intent, verification results, and test coverage, Applicants for employment at Blue Origin must be a U.S. citizen or national, U.S. permanent resident (i.e. current Green Card holder), or lawfully admitted into the U.S.as a refugee or granted asylum.

Background Check

• Required for all positions: Blue’s Standard Background Check
• Required for Certain Job Profiles: Defense Biometric Identification System (DBIDS) background check if at any time the role requires one to be on a military installation
• Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs. and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing, vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training.
• Required for certain Job Profiles: Ability to obtain and maintain Merchant Mariner Credential, which includes pre-employment and random drug testing as well as DOT physical

• BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year)
• Coursework or project experience with Verilog/SystemVerilog RTL design or verification
• Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing)
• Familiarity with basic verification concepts (testbenches, simulation, coverage)
• Strong problem-solving skills and attention to detail
• Effective communication and ability to work in a collaborative team environment

Desired:

• Academic or internship experience with SystemVerilog/UVM
• Exposure to scripting languages (Python, Perl, Tcl) for automation/tooling
• Coursework or projects involving communications systems, DSP, or FPGA design
• Familiarity with common EDA tools (e.g., VCS, Xcelium, Questa, formal tools)
• Understanding of computer architecture fundamentals (CPUs, bus protocols like AXI)
• Personal projects, capstone work, or research involving digital design/verification (e.g., GitHub repos, senior design projects)

$129,032.00-$180,644.10 life insurance, parental leave, paid time off, paid holidays, 401(k), stock options, * Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.

• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company’s intent to reward individual contributions and enable them to share in the company’s results, or other factors at the company’s sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.