Digital Verification Engineer (1-5 Year's Experience)

We have an exciting opportunity for Digital Verification Engineer (1-5 Years’ Experience) to join an innovative team developing high-quality open-source silicon used in production devices.

Location: Cambridge, UK (Hybrid)

Position: Permanent

About the Role

Working on projects such as OpenTitan Root of Trust and Ibex RISC-V CPU, you’ll collaborate with world-leading partners and apply industry-standard verification methodologies to cutting-edge silicon designs.

As a Digital Verification Engineer, you’ll contribute to the verification of complex digital designs at both block and system level. You’ll work alongside experienced engineers, helping to develop robust verification environments while gaining exposure to production silicon and advanced verification methodologies.

Responsibilities

• Develop and debug SystemVerilog/UVM testbenches.
• Create and execute verification plans, tests, and coverage.
• Debug simulation failures and support regression testing.
• Contribute to verification infrastructure and automation.
• Collaborate closely with design engineers to ensure high-quality silicon.
• Participate in code reviews and contribute to open-source projects.

Requirements

• 1-5 years’ industry experience in Digital Design Verification.
• Experience with SystemVerilog and UVM.
• Understanding of verification methodologies and constrained-random verification.
• Experience writing testbenches and debugging RTL.
• Programming experience in Python and/or C.
• Familiarity with Git or other version control systems.
• Strong communication skills and a collaborative mindset.
• Exposure to RISC-V or CPU verification.
• Knowledge of formal verification.
• Experience with scripting and verification automation.
• Interest in open-source hardware and silicon development.

What’s on Offer?

• Collaborate with globally recognised semiconductor partners.
• Excellent learning and career development opportunities.
• Join a highly collaborative engineering team working on technology that is shaping the future of semiconductor design.

• 1-5 years’ industry experience in Digital Design Verification.
• Experience with SystemVerilog and UVM.
• Understanding of verification methodologies and constrained-random verification.
• Experience writing testbenches and debugging RTL.
• Programming experience in Python and/or C.
• Familiarity with Git or other version control systems.
• Strong communication skills and a collaborative mindset.
• Exposure to RISC-V or CPU verification.
• Knowledge of formal verification.
• Experience with scripting and verification automation.
• Interest in open-source hardware and silicon development.

• Collaborate with globally recognised semiconductor partners.
• Excellent learning and career development opportunities.
• Join a highly collaborative engineering team working on technology that is shaping the future of semiconductor design.