Staff Digital Design Engineer

RENESAS ELECTRONICS AMERICA INC.
Chandler, AZ, United States
9 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
10 years minimum
Working hours
Regular working hours
Languages
English
Job source

Tech stack

Communications Protocols Computer Engineering Microarchitecture Data Conversion Software Debugging Software Design Documents Digital Electronics Logic Synthesis of Circuits Formal Verification Hardware Design Static Timing Analysis SystemVerilog
+7 more
Systems Integration Test Case Verilog Scripting Application Specific Integrated Circuits Information Technology Power Analysis (Cryptography)

Job description

Renesas Electronics is seeking a highly skilled and motivated Staff Digital Design Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications.

Job Purpose & Dimensions:

· Interpret high level requirements to architect, design & integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.

· Support full product lifecycle from concept to mass-production; communicating closely with wider organization through the various stages of silicon development.

· Provide technical leadership & influence to the digital design team by contributing to technical discussions & reviews, mentoring junior engineers, and supporting recruitment.

· Work closely with Analog and Verification engineers to deliver high-quality silicon solutions.

Responsibilities:

· Ensuring digital development process is state-of-art and achieves budget, schedule, and project deliverable goals.

· Designing digital RTL that meets timing, area, power and any adhering standards specifications.

· Integrating design at the top level and running block & top-level simulations.

· Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF.

· Working closely with P&R team to generate a layout that meets timing, area, and power requirements.

· Support DFT strategy and implementation, and review test case development.

· Assisting with top level test-bench debug, and running RTL & gate level simulations

· Working with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification.

· Supporting analog team to develop AMS, System Verilog or Verilog-real behavioral models.

· Developing detailed block & chip level design documents and collateral.

· Holding and participating in key design reviews and completion of various checklists.

· Perform silicon evaluation as required.

· Document device errata, develop work-around solutions, implement engineering changes when necessary.

Requirements

· >10 years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management.

· Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.

· Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design.

· Strong understanding of ASIC design methodology.

· Strong understanding of Lint, CDC & RDC tools.

· Strong understanding of block-level & chip-level verification techniques.

· Strong & proven ability to debug both RTL & gate-level simulations.

· Mandatory competence in written and verbal English.

· Willingness to travel domestically or internationally on short notice.

· Ability to work independently and collaboratively.

· Preferred: experience with Digital Signal Processing (DSP) concepts and hardware realizations.

· Preferred: experience with methodology and flow automation using appropriate scripting.

· Preferred: experience with mixed-signal design methodologies.

· Preferred: experience developing design constraints and hand-off to P&R.

· Preferred: experience with STA and timing closure.

· Preferred: experience with low-power design techniques, including clock and power gating (UPF).

· Preferred: experience with power analysis and optimization.

· Preferred: experience with advanced verification methodologies (UVM).

· Preferred: experience with industry-standard protocols such as AMBA or I2C.

About the company

Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.

With a diverse team of over 22,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’

At Renesas, you can:

  • Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
  • Make a real impact by developing innovative products and solutions to meet our global customers’ evolving needs and help make people’s lives easier, safe and secure.
  • Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.

Are you ready to own your success and make your mark?

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