Sr Digital Design Engineer

We are seeking a highly skilled and analytical Senior FPGA/Digital Design Engineer to join our team. In this role, you will bridge the gap between high-level modeling and hardware realization, specifically focused on translating complex MATLAB algorithms into optimized Verilog code. You will play a critical role in defining hardware interfaces between FPGAs and digital drive circuitry, as well as designing and optimizing hybrid drive-sense architectures. The ideal candidate will possess deep expertise in timing architecture design, hardware optimization, and maintaining an intimate knowledge of the current state of the technology to drive critical component selection and engineering decisions., * Algorithm-to-Hardware Translation: Translate, refactor, and implement complex MATLAB/Simulink algorithms into efficient Verilog/SystemVerilog code for FPGA deployment.

• Interface Definition & Design: Define, document, and implement robust digital communication interfaces and protocol layers between high-speed FPGAs and peripheral digital/analog drive circuitry.
• Hybrid Drive-Sense Systems: Design and integrate digital logic for complex hybrid drive-sense architectures, ensuring precise synchronization, signal integrity, and low-latency feedback loops.
• Timing Architecture & Closure: Architect and implement comprehensive clocking and timing structures, managing multi-clock domain crossings (CDC) and achieving strict timing closure on high-utilization designs.
• Hardware Optimization: Analyze and optimize FPGA resources (LUTs, DSPs, BRAMs) and code performance to improve key metrics such as throughput, latency, power consumption, and clock frequency.
• Component Selection & Architecture: Leverage deep familiarity with the current state of technology (FPGA families, ADCs/DACs, high-speed drivers) to conduct trade studies, select appropriate hardware components, and make critical engineering decisions.
• Verification & Validation: Develop testbenches and simulation frameworks to validate Verilog RTL against MATLAB golden models, and perform hands-on hardware bring-up and debugging using lab equipment (oscilloscopes, logic analyzers).

Do you have experience in FPGA?, Do you have a Master’s degree?, * Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related technical field.

• 5+ years of experience in FPGA/ASIC design, verification, and implementation using Verilog or SystemVerilog.
• Proven experience manually translating and optimizing algorithms from MATLAB/Simulink into hardware-efficient RTL.
• Strong background in timing architecture design, including constraint generation (SDC/XDC), static timing analysis (STA), and clock domain crossing mitigation.
• Hands-on experience interface-mapping and integrating FPGAs with external digital/analog circuitry (e.g., SPI, I2C, PCIe, or custom high-speed parallel buses).

Preferred Requirements

• Experience designing hybrid mixed-signal or drive-sense circuitry loops (e.g., precision beam steering, high-density optical networking controls, or autonomous robotics sensing).
• Deep understanding of modern FPGA architectures (e.g., AMD/Xilinx UltraScale+, Intel Stratix/Agilex) and advanced toolchains (Vivado, Quartus Prime).
• Familiarity with hardware/software co-design, embedded processors (e.g., ARM Cortex, MicroBlaze), or SoC architectures.
• Demonstrated track record of leading component-selection trade studies for aerospace, defense, or high-reliability commercial hardware environments.
• Experience with automated MATLAB HDL Coder workflows, complemented by the ability to write clean, hand-optimized RTL when automated tools fall short.

Pulled from the full job description

• 401(k)
• Health insurance
• Retirement plan
• 401(k) matching
• Paid time off
• Vision insurance
• Health savings account, * 401(k)
• 401(k) matching
• Dental insurance
• Flexible schedule
• Health insurance
• Health savings account
• Life insurance
• Paid time off
• Retirement plan
• Vision insurance