ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)

Experteer Overview As an ASIC/FPGA Methodology Engineer, you define and maintain methodologies for FPGA/ASIC design and verification in a Linux-based environment. You will collaborate with design and verification teams to streamline workflows and optimize RTL/debug processes. You drive design flow improvements for FPGA tools and implement CI/CD pipelines, while guiding teammates on best practices. This role supports cutting-edge hardware development aligned with Teradyne’s mission to enable reliable product manufacturing at scale. Compensation / Benefits * Develop and maintain ASIC/FPGA design, verification, and implementation methodologies * Collaborate with design and verification teams to integrate workflows and tools * Support RTL design work using Verilog and assist in debugging hardware issues * Optimize FPGA design flows for tools like Vivado, Quartus * Implement and manage CI/CD pipelines using Jenkins, Docker, and Git * Utilize Linux utilities (Git, Docker, LSF, Clearcase) to support workflows * Provide technical guidance and training on FPGA/ASIC methodologies * Stay updated on industry trends to improve design methodologies Tasks * Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field * 3+ years in FPGA and embedded design * Strong understanding of FPGA and embedded design principles * Hands-on experience with Vivado and Quartus * Familiarity with ASIC design flows and methodologies * Proficiency with Git, Docker, LSF, Jenkins, Artifactory, Clearcase * Knowledge of CI/CD workflows and automation tools * Understanding of SystemVerilog and UVM for digital design verification * Experience with timing analysis, synthesis, and timing closure * Familiarity with system-level integration and validation * Strong problem-solving and debugging skills Key requirements * medical, dental, vision * Flexible Spending Accounts * retirement savings plans * life and disability insurance * paid vacation & holidays * tuition assistance

_ support workflows * Provide technical guidance and training on FPGA/ASIC methodologies * Stay updated on industry trends to improve design methodologies Tasks * Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field * 3+ years in FPGA and embedded design * Strong understanding of FPGA and embedded design principles * Hands-on experience with Vivado and Quartus * Familiarity with ASIC design flows and methodologies * Proficiency with Git, Docker, LSF, Jenkins, Artifactory, Clearcase * Knowledge of CI/CD workflows and automation tools * Understanding of SystemVerilog and UVM for digital design verification * Experience with timing analysis, synthesis, and timing closure * Familiarity with system-level integration and validation * Strong problem-solving and debugging skills Key requirements * medical, dental, vision * Flexible Spending Accounts * retirement savings plans * life and disability insurance * paid vacation & holidays * tuition a workflows