Senior Technical Architect

Leads block-level and top-level physical implementation, driving design closure from netlist to GDS while coordinating cross-functional teams. Also owns full-chip integration activities., * Manage floorplanning, placement, CTS, routing, and signoff closure

• Drive PPA (Power, Performance, Area) optimization
• Full-chip assembly and hierarchical integration
• Resolve timing, congestion, IR, EM, DRC/LVS issues
• Coordinate with RTL, STA, DFT, Package, and Verification teams
• Tape-out planning and execution
• Mentor physical design engineers

• Strong expertise in Synopsys ICC2/Fusion Compiler or Cadence Innovus
• Advanced floorplanning and partitioning knowledge
• Timing closure expertise
• Full-chip integration and hierarchical design methodologies
• TCL, Perl, Python scripting
• Excellent debugging and stakeholder management skills
• Experience with advanced process nodes (16nm and below preferred)