Senior Technical Architect

STA Lead, Owns timing signoff methodology and ensures timing closure across blocks and full-chip., * Support tape-out activities

• Define STA signoff methodology
• Setup/hold closure
• MMMC scenario management
• Constraint development and validation
• Timing ECO generation and validation
• Cross-domain timing analysis
• SI (Signal Integrity) and OCV analysis
• Timing signoff reviews and tape-out approval

• PrimeTime expertise (PT, PT-SI, PBA)
• Deep understanding of timing constraints (SDC)
• MMMC and variation modeling concepts
• Crosstalk and noise analysis
• Clock architecture knowledge
• Statistical timing concepts (AOCV, POCV)
• Strong scripting capability (TCL, Python)