Staff Design Engineer

• Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan - collaborating with circuit and block-level layout designers on sizing, pin rings, inter-block routing, and full-chip channels - while maintaining order in layout hierarchy for streamlined development and tape-in
• Work closely with the analog and digital design teams on floor planning, pin placement, power supply strategy and signal distribution between blocks
• Coordinate with program managers and cross-functional teams - design, verification, packaging, manufacturing, and foundry - to track layout and floorplan activities to a predictable schedule and lead a successful, timely and quality tape-out
• Conduct layout reviews for power/ground routing, electromigration, matching, and signal coupling/integrity, and complete full-chip closure activities, including seal-ring and bump integration, dummy fill, DRC, LVS, density, and DFM checks
• Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks for both high-performance RF as well as ultra-low power and compact RFID
• Participate in the IC layout methodology roadmap, collaborating with technology, CAD, and design teams to ensure successful deployment while balancing short-term execution with long-term strategic goals

• Bachelor’s or master’s degree in computer or electrical engineering or a related technical field, with 12+ years of experience
• Experience in custom analog, RF, and mixed-signal layout, with ability to lead complex ICs from conception to tapeout
• Versed in tapeout flows with experience in final database preparation and tapeout checklists
• Ability to lead and mentor other layout engineers as the top-level floorplan/IC integration owner, partnering with circuit designers to resolve complex problems
• Expert in full-chip/SOC-level floorplanning and integration - physical implementation of cells and analog blocks/IPs, pin-ring generation, routing management, and full-wafer assembly - with experience delivering advanced floorplan strategies and debugging DRC/LVS verification across intermediate hierarchies and at the full-chip level, for both analog-on-top (AOT) and digital-on-top (DOT) methodologies
• Understanding of semiconductor manufacturing processes and foundry technologies across advanced process nodes down to 16nm for ultra-low-power and high-fidelity applications
• Understanding of analog layout challenges and layout-dependent effects in advanced processes - noise coupling, matching, parasitics, LOD, WPE, PSE, and coloring - along with proficiency in mitigation techniques such as guard rings, DNW, PN junctions, parasitic management, signal integrity, reliability (EMIR), and ESD. Expert knowledge of Cadence Virtuoso schematic and layout editors, plus Cadence/Siemens layout verification tools (including PVS and Siemens Calibre DRC/LVS), with strong proficiency interpreting and correcting ERC, DRC and LVS error reports
• Strong communication skills to effectively collaborate with cross-functional teams and external partners
• Demonstrated strong technical project management skills with the ability to prioritize tasks, anticipate roadblocks, manage schedules, and deliver results in a fast-paced environment

The typical base pay range for this role across the US is $158,700 - $238,100. Individual base pay depends on various factors such as complexity and responsibility of role, job duties, requirements, and relevant experience and skills. Both market wage data and the mid-point of the pay range is reviewed and used as the starting point for all new hire offers. Offers are made within the base pay range applicable at the time.

At Impinj certain roles are eligible for additional rewards, including merit increases, annual bonus and stock. These awards are allocated based on individual performance. In addition, certain roles also have the opportunity to earn sales incentives based on revenue or utilization, depending on the terms of the plan and the employee’s role. US based employees have access to healthcare benefits; a 401(k) plan and company match among others., Know you’re making a difference. Competitive benefits. Support for remote work or a desk with a view. Weekly Q&A sessions with our executive team. Impinj provides an environment that fosters openness and innovation and is developing technology that delivers a positive impact on the world. Collaboration and teamwork are highly valued, and accomplishments are duly celebrated. We have an open paid time-off policy paired with a respect for work/life balance. Our headquarters is located in Seattle with spectacular views of the Olympics, Lake Union, and Mt Baker, which can be enjoyed from our rooftop deck. Our Brazilian site is in Porto Alegre, Rio Grande do Sul state, at “Tecnopuc,” a technology park that offers a very nice workplace for the development of groundbreaking technologies. Impinj is committed to creating a diverse and inclusive work environment and welcomes applicants from all backgrounds.

The Layout Design Engineering group is an integral part of the Silicon Engineering department, working closely with the analog RFID end-point IC development team and the Reader IC team, internationally. The team is responsible for delivering tape-outs for RFID products, test chips, reader ICs, and DOEs (design of experiments) work that sits at the center of how Impinj brings new silicon to market.

Layout decisions made by this team directly influence the power efficiency, cost, and time-to-market of every piece of silicon we ship, making the group’s work foundational to Impinj’s mission. The team operates with a continuous-improvement mindset, adapting quickly and challenging each other to remain best-in-class in both quality and speed, with meticulous attention to detail to ensure designs have long-term reliability and zero defects, at production volumes in the many billions and eventually trillions of tags per year.