SoC Front-End Lead

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management., We are seeking a highly skilled and collaborative SoC Front-End Lead to spearhead the technical direction, micro-architecture, and logic design of our next-generation semiconductor products. In this role, you will bridge the gap between high-level architectural requirements and physical reality, managing the front-end execution from micro-architecture to netlist delivery. You will lead a talented team of hardware design engineers and partner with cross-functional teams including Emulation and Firmware to deliver high-performance, low-power silicon.

What you’ll do

• Technical Leadership & Team Management: Lead, mentor, and scale the front-end design team. Set design methodology, coding standards, code-review processes, and execution timelines.
• Micro-Architecture & Block Partitioning: Translate product requirements into detailed micro-architectural specifications. Own block partitioning, data flow, and interface standards across the chip front-end.
• IP & SoC Integration: Oversee the integration of internal and third-party IP blocks (e.g., PCIe, UCIe, CXL etc). Manage the integration of core pervasive logic including clocking, resets, pad rings, and power management (UPF).
• AI-Driven Design Automation: Evaluate, pilot, and deploy AI-powered design assistants and LLM copilots within the RTL generation, code review, and documentation workflows to accelerate design velocity.
• Front-End Signoff Discipline: Ensure quality and signoff readiness across the front-end using static verification tools (Linting, Clock Domain Crossing/CDC, Reset Domain Crossing/RDC, and Logical Equivalence Checking/LEC).
• Physical Closure Collaboration: Partner closely with physical design (back-end) teams to address timing constraints, area optimization, and floorplanning awareness early in the design cycle.
• Verification & DFT Alignment: Work alongside Design Verification (DV) teams to define testing plans and coverage strategies. Collaborate with Design for Test (DFT) leads to inject scan-friendly structures and debug hooks into the RTL.
• Silicon Bring-Up: Act as a key technical contact during post-silicon laboratory bring-up, debugging, and issue triage.

If you’re reading this, you’re probably comfortable. You have a good job at a stable company with all the benefits., * Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.

• Experience: 12+ years of digital design and RTL development experience, with a proven track record of delivering complex, production-grade SoCs.
• Hardware Description Languages: Expert proficiency in SystemVerilog or Verilog for high-performance design.
• Methodology Tools: Hands-on experience with industry-standard front-end tools (e.g., Synopsys SpyGlass, VC Formal, Cadence JasperGold) for Lint, CDC, and formal checks.
• Architecture Knowledge: Deep understanding of digital design fundamentals, clock/reset structure design, and power intent specification (UPF/CPF).
• Soft Skills: Exceptional cross-functional communication skills to coordinate between architecture, physical design, firmware, and software teams.

Good to Have

• Experience with high-speed protocols or fabric interconnects (e.g., PCIe Gen6+, CXL, CHI, or UCIe chiplet interfaces).
• Familiarity with advanced semiconductor process nodes (e.g., 5nm, 3nm, or below).
• Proficiency in scripting languages (Python, Perl, or Tcl) to automate design flows

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That’s what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale., * The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we’re building.

• The team has done this before. We’ve built and exited semiconductor companies at scale. This isn’t our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You’re not optimizing someone’s ad click-through rate. You’re building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you’re the kind of person who wants to take the shot, we’d love to talk., The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.