Senior FPGA Engineer

We are looking for a Senior FPGA Engineer to take technical ownership of that gateware: someone who can shape architecture from system requirements, raise the bar on design and verification quality, and grow the engineers around them.

You will join a development teams built around a specific unit: on-board computers, software defined radios, image sensors, optical transceivers, network switches or telecommunication payload and act as the FPGA technical reference for that team. Beyond writing RTL yourself, you will own the FPGA architecture, make and defend the key design trade-offs, mentor junior and mid-level engineers, and lead small groups of FPGA engineers on the more complex units.

These units bring challenging signal and image processing algorithms, innovative optical solutions and high-throughput routing. Communication and cooperation across competences are central: you’ll work closely with PCB designers (EE) and embedded software engineers, and, depending on the project: RF, optical or network engineers. You’ll often be the person translating between system intent and gateware reality.

Expect a role where your decisions shape state-of-the-art gateware that rapidly makes its proof in orbit.

Missions: Answer challenging requirements with innovative, well-justified architectural solutions Cope with the constraints of the space environment Create critical, high-quality gateware and the verification that proves it Set and uphold design, documentation and verification standards across the team Mentor FPGA engineers and lead small FPGA teams on complex units

Work Environment: RTL: VHDL Simulation: Questasim, Makefile, Python, TCL Tests on target: Makefile, Embedded-C, Embedded-Linux, FreeRTOS, Python CI/CD: Gitlab, Docker

Key Activities: Define and own the FPGA design architecture from system requirements, including the major design trade-offs Design, simulate, integrate and test RTL code while reviewing the RTL of others Drive the verification strategy (testbenches, on-target test procedures, CI) Write and test software driver code Write and review technical documentation Mentor junior and mid-level engineers, and lead small FPGA teams Interface with other engineering teams (EE, RF, Operations, Embedded Software, System) and represent FPGA in cross-unit technical decisions

5 to 10 years of professional experience in FPGA/RTL design, with a track record of taking designs from requirements through to validated hardware Master or PhD in Computer, Electronics or Mechatronics Engineering or equivalent through experience Strong command of RTL programming (in order of preference: VHDL, Verilog, SystemC, SystemVerilog) Experience with C and Python Strong understanding of the full FPGA design flow (synthesis, place & route, timing closure) Strong understanding of software and hardware interactions Solid experience with version control and continuous integration Experience with digital signal or image processing Proven ability to mentor engineers and provide technical leadership Excellent verbal and written skills to interact across teams and up to system level Comfortable in a lab environment: power supplies, oscilloscopes and spectrum analyzers Good English knowledge Passion for digital design

Nice To Have

Experience in space or another high-reliability / safety-critical domain (avionics, automotive, medical) Familiarity with radiation effects and mitigation techniques (TMR, scrubbing, etc.) Experience with Embedded-Linux (CLI usage & kernel customization) Experience with high-speed transceivers, PCIe or network interfaces (1G to 100G) Experience with memory interfaces (DDR3, DDR4, DDR5) Experience with PCB and hardware design Experience with advanced or formal verification methodologies