Senior FPGA Engineer (VHDL/Verilog)

Must-have

• Master’s degree in electronics engineering, or similar by experience.
• Strong knowledge of VHDL and Verilog development. Programming skills in Tcl and Python.
• Experience in timing analysis and closure.
• Experience with unit simulation testing and test automation (Jenkins).
• Familiar with working in a Linux environment. Understanding of networking concepts (Ethernet, TCP/IP, MAC addressing, buffering, etc.).
• Strong problem-solving and debugging skills. Eagerness to familiarize yourself with new and cutting-edge technologies.

Nice-to-have

• Familiar with Xilinx FPGA tools and QuestaSim/ModelSim.
• Experience working with Cocotb verification environment.
• Knowledge of high-speed interfaces: DDR4, Ethernet, PCIe, AXI4, AXI-lite.