Silicon Design Manager, RTL Machine Learning, Accelerator Design

As a Silicon Design Manager, you will develop high-performance and low-power hardware to enable continuous innovations in the Tensor Processing Unit (TPUs). In this role, you will work with Architects to drive architectural feasibility, establish timing design goals, and explore trade-offs for physical design closure. You will also work with Software teams to understand and implement clocking and power management requirements., * Lead, mentor, and manage a team of RTL Design Engineers performing tasks related to IP development for Compute Cores.

• Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.).
• Serve as the primary point of contact for all design-related activities on projects. Participate with Architecture and System Design teams in architecture definition, IP area estimation, power optimization, and performance enhancements.
• Collaborate closely with cross-functional teams (e.g., Verification, Design for Test, Physical Design, and Software) to make design plans and present project status throughout the development cycle.
• Drive improvements in design methodologies, processes, and quality control measures.

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Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

Share Silicon Design Manager, RTL Machine Learning, Accelerator Design, * Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
• 8 years of experience in Computer Architecture and Register-Transfer Level.
• 3 years of experience in people management and developing employees., * Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Knowledge of high performance and low-power design techniques.
• Knowledge of ASIC Verification, Design For Testing (DFT), Synthesis, Static Timing Analysis (STA), or Physical Design.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving force behind Google’s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits