Cryptography Engineer

About the RoleWe are seeking an experienced Digital Design Engineer with a passion for hardware security, cryptography, and secure silicon design. This is an opportunity to work on cutting-edge security technologies for next-generation connected devices, developing highly optimized cryptographic hardware for ASIC and FPGA platforms. You will contribute across the full digital design lifecycle, from architecture and RTL development through verification, synthesis, timing closure, and silicon implementation. Working alongside hardware, verification, and embedded software teams, you will help deliver secure, high-performance solutions for resource-constrained environments. What You’ll Be DoingDesign, develop, and verify secure digital hardware modules for ASIC and FPGA implementations.Implement and optimize cryptographic algorithms and security primitives including AES, SHA, and True Random Number Generators (TRNGs).Develop efficient architectures optimized for area, power consumption, memory footprint, and performance.Apply secure hardware design methodologies and implement countermeasures against side-channel attacks.Participate in the complete development flow including specification, architecture definition, RTL design, synthesis, static timing analysis (STA), formal verification, and validation.Collaborate closely with hardware, firmware, software, and verification teams to integrate security functionality into complex systems.Develop Python-based automation, verification, and analysis tools to improve design productivity and quality.Contribute to technical discussions, architectural decisions, and continuous improvement of secure hardware design practices. Required Experience5+ years of industry experience in digital hardware design, or 2+ years of industry experience combined with a PhD in Cryptography, Hardware Security, or a related field.Strong understanding of cryptographic algorithms and their hardware implementations, including both symmetric and asymmetric cryptography.Proven experience designing and optimizing digital systems for low-power and resource-constrained environments.Expertise in Verilog and/or VHDL development.Strong understanding of RTL design methodologies, simulation, verification, and testbench development.Experience with ASIC and FPGA development flows.Practical knowledge of synthesis, timing analysis, and hardware verification techniques.Strong analytical and debugging skills with the ability to solve complex technical challenges.Excellent communication skills and the ability to collaborate within distributed engineering teams. QualificationsBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.Deep understanding of digital design principles and secure hardware architectures.Experience using Python or similar scripting languages for automation, analysis, and verification workflows.Comfortable working in a fast-paced environment with evolving technical requirements. Nice to HaveExperience implementing Post-Quantum Cryptography (PQC) algorithms in hardware.Knowledge of Root of Trust architectures, Secure Elements, Hardware Security Modules (HSMs), and Secure Boot technologies.Exposure to RISC-V processor architectures and microarchitecture concepts.Familiarity with side-channel analysis techniques and hardware countermeasure implementations.Experience with formal verification methodologies and security-focused hardware validation.

Why Join?Fully remote working environment.Work on advanced hardware security and cryptographic technologies.Opportunity to influence architecture and technical direction.Collaborative engineering culture with significant ownership and autonomy.Exposure to cutting-edge ASIC, FPGA, and secure silicon development.Competitive salary, benefits, and long-term growth opportunities.2 x Teams calls for an asap start KeywordsHardware Security | ASIC | FPGA | RTL Design | Verilog | VHDL | Cryptography | AES | SHA | TRNG | Secure Boot | Root of Trust | HSM | Post-Quantum Cryptography | RISC-V | STA | Formal Verification | Python