DFT DV Engineer, AI Hardware

Our Silicon Engineering team validates DFT features from RTL through silicon bring-up - ensuring test structures work correctly before the chip reaches the tester. As a Staff DFT DV Engineer, you will own functional verification of all DFT structures at block and SoC level, delivering pre-Si testcases that directly enable silicon debug and ATE correlation. What You’ll Do

• DevelopSystemVerilog/UVM testbenches to verify DFT features - SSN, compressed scan, memory BIST, JTAG, and boundary scan at block and SoC level
• Verify top-level DFT features - power-on self-test, clock observation, clock stop, and scan dump
• Run DV regressions, analyze coverage,triageand debug failures to closure
• Identifydesign fixes and validate DFT RTL corrections
• Deliver pre-Si DV testcases for silicon bring-up and ATE correlation
• Own post-silicon ATE test correlation - root cause discrepancies between pre-Si and silicon behavior
• Leverage agentic AI flows to automate regression execution, coverage analysis, and failure triage

• Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
• 3+ years of DFT DV experience at block and SoC level
• Expert-levelSystemVerilogand UVM testbench development
• Hands-on verification of SSN, compressed scan, MBIST, JTAG, and boundary scan
• Experience delivering pre-Si testcases through silicon bring-up and ATE correlation
• Ability to use agentic AI flows to automate DV regression and debug workflows
• Post-silicon debug and ATE correlation experience on server-class SoCs
• Familiarity with formal verification methods for DFT structural checks
• Experience with power-on self-test and clock control verification

Along with competitive pay, as a full-time Tesla employee, you are eligible for the following benefits at day 1 of hire:

• Medical plans > plan options with $0 payroll deduction
• Family-building, fertility, adoption and surrogacy benefits
• Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
• Company Paid (Health Savings Accounts) HSA Contribution when enrolled in the High-Deductible medical plan with HSA
• Healthcare and Dependent Care Flexible Spending Accounts (FSA)
• 401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
• Company paid Basic Life, AD&D
• Short-term and long-term disability insurance (90 day waiting period)
• Employee Assistance Program
• Sick and Vacation time (Flex time for salary positions, Accrued hours for Hourly positions), and Paid Holidays
• Back-up childcare and parenting support resources
• Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
• Weight Loss and Tobacco Cessation Programs
• Tesla Babies program
• Commuter benefits
• Employee discounts and perks program

Expected Compensation $128,000 - $312,000/annual salary + cash and stock awards + benefits

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence throughcutting-edgehardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla’s custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla’s AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Teslaremainsa leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla’s AI hardware team isseekinga highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom AI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our AI training and inference systems. This role emphasizesexpertisein tensor operations, matrix computations, and optimized data paths for advanced AI workloads.This role is located in Palo Alto, CA or Austin, TX. If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary AI hardware.