Wireless Design Verification Engineer

As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV methodologists, designers, and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric-driven verification, ensuring the highest design quality. Minimum Qualifications + Minimum requirement of a bachelor’s degree. Preferred Qualifications + 3+ years of verification experience of wireless/wired communication block/subsystem. + Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion. + Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. + Verification experience of one or more of the following: MAC, PHY, DMA, timer, AMBA bus and fabric, encryption/decryption engine. + Verification experience of wireless/wired communication block/subsystem. + Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee. + Proficient in shell and Python scripting, Perl scripting. + Experience of using AI technologies in data mining/analysis. + Experience of Palladium/FPGA validation. + Should be a team player with excellent communication skills, self-motivated and well organized.