Wireless Design Verification Engineer

APPLE WIRELESS
Irvine, CA, United States
5 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
10 years minimum
Working hours
Regular working hours
Job source

Tech stack

Communications Protocols Formal Verification Subsystems SystemVerilog Application Specific Integrated Circuits Integration Frameworks Hardware Acceleration

Job description

You’ll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Senior Wireless Design Verification Engineer, you’ll ensure first-time-right silicon success through sophisticated testbenches, comprehensive scenarios, and cutting-edge verification methodologies-enabling multi-gigabit wireless technology connecting the world! Description As a Senior Wireless Verification Engineer, you will be at the core of our wireless product’s success, bridging domains, driving collaborations, and developing verification solutions to ensure excellent products. You will lead verification of controllers, datapaths, subsystems, protocols, low power capabilities, and SOC / integration frameworks. You will leverage and architect environments, develop scenarios, and utilize metrics.

Requirements

You’ll develop verification strategies for wireless features enabling advanced applications across Apple’s product ecosystem. Minimum Qualifications + BS and a minimum of 10 years relevant industry experience. + Demonstrated expertise verifying complex digital ASICs with track record of successful silicon tapeouts. + Deep knowledge of ASIC verification flows with SystemVerilog and UVM including testbench architecture, verification planning, and coverage-driven methodologies. + Experience developing verification environments from scratch and bringing up complex designs in simulation. + Experience with constrained random testing, functional coverage, and assertion-based verification. Preferred Qualifications + Exposure to ASIC architectures including datapath operation, processing / hardware acceleration, and/or low-power mechanisms. + Experience with applying system-models, DPI integration, bus functional models (BFMs), transaction-level modeling, and verification IP development. + Proficiency in Python scripting for automation, metric analysis, and general infrastructure development. + Technical leadership through example-driving verification strategies, establishing best practices, and delivering complex projects. + Nice to have - exposure to formal verification, low-power methodologies, communication protocols, and/or analytical problem solving. + Experience with large-scale regression infrastructure frameworks. + Excellent communication skills and ability to influence cross-functional technical decisions.

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