Senior Semiconductor Test Engineer

As a Senior Test Engineer, you will lead the development and execution of test strategies for our Multi-Chip Module (MCM) and System-in-Package (SiP) products. You will be responsible for translating semiconductor datasheets into comprehensive test plans, developing automated test programs, and helping architect the test infrastructure that supports our growing product portfolio., * Translate semiconductor datasheets, timing diagrams, and electrical specifications into test plans and automated test programs.

• Develop validation methodologies for digital, analog, mixed-signal, RF, and power devices.
• Create and maintain test specifications, test procedures, and qualification documentation.

Build and Scale Test Infrastructure

• Help architect, implement, and maintain a PXI-based modular test platform using National Instruments or equivalent technologies.
• Select instrumentation including DMMs, oscilloscopes, digital I/O, power supplies, switching systems, and related hardware.
• Define test fixture, interface board, and connectivity requirements for products under test.

Drive Test Automation

• Develop, debug, and optimize automated test software using LabVIEW, TestStand, Python, and related frameworks.
• Implement functional, parametric, characterization, and production test coverage.
• Improve test efficiency, repeatability, and scalability across product lines.

Lead Validation and Characterization

• Perform correlation studies, guard band analysis, and test coverage assessments.
• Support product characterization and qualification activities.
• Investigate failures and drive root-cause analysis at the component, interconnect, board, and module level.

Collaborate Across Engineering Disciplines

• Partner closely with design, product, package, quality, and manufacturing engineers.
• Contribute to design-for-test (DFT) discussions and new product introduction (NPI) activities.
• Support continuous improvement of validation processes and standards.

Develop Advanced Test Strategies

• Design and execute boundary scan (JTAG/IEEE 1149.1) testing strategies.
• Develop test methodologies for MCM and SiP architectures, including interconnect verification, thermal considerations, and system-level validation.
• Contribute to future Known Good Die (KGD) testing initiatives.

• Experience designing and deploying a complete test system from concept through production.
• Familiarity with Known Good Die (KGD) methodologies and multi-die validation strategies.
• Experience with semiconductor qualification and reliability testing, including burn-in, temperature cycling, humidity testing, ESD, and related evaluations.
• Knowledge of package and interconnect technologies including wire bond, flip-chip, and SMT assembly.
• Understanding of PCB manufacturing and inspection processes, including AOI, X-ray, and flying probe testing.
• Experience collaborating on Design-for-Test (DFT) implementations.
• Familiarity with version control systems, test data management, and reporting tools.
• Exposure to Six Sigma, reliability engineering, or quality systems methodologies.
• Failure analysis experience involving X-ray, CSAM, cross-sectioning, curve tracing, or similar techniques.
• Knowledge of semiconductor ATE platforms such as Teradyne or Advantest.