STA Engineer

Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment

Experience in design automation using TCL/Perl/Python.

Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus

Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.

Education:

B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.

Preferred Qualification/Skills

Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling

Hands-on experience with STA tools - Prime-time, Tempus

Have experience in driving timing convergence at Chip-level and Hard-Macro level

In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,

Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)

Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.

Proficient is scripting languages - TCL, Perl, Awk

Basic knowledge of device physics