STA/Constraints Engineer

Advanced Micro Devices, Inc.
Santa Clara, CA, United States
5 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Job source

Tech stack

Computer-Aided Design Artificial Intelligence Perl (Programming Language) Static Timing Analysis Subsystems Tcl (Programming Language) Verilog Scripting Application Specific Integrated Circuits Physical Verification Physical Design

Job description

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers., * Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.

  • Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
  • Understanding clock design requirements and making sure they are correctly set up in SDC.
  • Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
  • Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
  • Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
  • Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
  • Work on SDC development, STA (Static Timing) analysis, shift left of timing closure, CDC (Clock Domain Crossing)., AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

Requirements

  • Industry experience in STA, constraints and timing signoff.
  • Expert user of industry-standard PD tools like SNPS PTA (must) and ICC2/FC (desired).
  • Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
  • Excellent presentation and inter-communication skills.
  • Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
  • Experience with physical design is a plus.
  • Has Synthesis or physical implement experience.
  • Experience with lower power design methodology.
  • Good English skills on talking, presentation and writing documents.
  • Good communication and strong sense of responsibility, task scheduling, and time management., * Bachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

About the company

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

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