Security Architect, Physical AI SoC

Auradine, Inc.
Santa Clara, CA, United States
3 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
10 years minimum
Working hours
Regular working hours
Job source

Tech stack

Artificial Intelligence Cyber Security Computer Engineering Software Debugging Federal Information Processing Standards (FIPS) Firmware Hardware Security Module Key Management Machine Learning System Software Delivery Pipeline Information Technology
+1 more
U-Boot

Job description

Role Overview Velaura is designing the compute silicon that will power the next generation of robots, autonomous systems, and intelligent machines operating in the physical world. As Security Architect for our Physical AI System-on-Chip (SoC), you will own the end-to-end security architecture of our silicon platforms- defining how our chips protect the AI models, sensor data, and safety-critical functions that Physical AI systems depend on. This is a foundational, cross-cutting role. You will set the hardware security strategy from the earliest architecture phase through tape-out and production, working across the silicon, firmware, platform software, and product teams. Because Physical AI systems act on the world-moving, sensing, and making autonomous decisions, the security of our SoC is inseparable from its safety. You will help ensure that Velaura silicon can be trusted in the field, at scale, and over its full lifecycle. Responsibilities

Own the SoC security architecture: define the hardware root of trust, secure boot, key management, secure debug, and lifecycle/provisioning strategy across Velaura’s Physical AI silicon roadmap. Architect protection for AI workloads and sensitive assets on-chip-model confidentiality and integrity, secure AI/NPU execution, memory isolation, trusted execution environments, and cryptographic acceleration. Lead threat modeling and security risk assessments for the SoC and its subsystems, translating attacker capabilities (physical, side-channel, fault-injection, supply-chain) into concrete hardware and firmware requirements. Partner with silicon design, firmware, safety, and platform software teams to embed security requirements into the RTL, boot flow, and SDK-and to review implementations against the architecture. Define the approach to secure updates, attestation, and device identity so that fielded Physical AI systems remain trustworthy throughout their operational lifetime. Establish security architecture standards, review processes, and design practices; mentor engineers and raise the security bar across the organization. Guide alignment with relevant security and functional-safety standards and support certification, audit, and customer security-assurance efforts.

Requirements

10+ years in security engineering or architecture, with significant experience defining hardware/SoC security for shipping silicon or embedded platforms. Deep expertise in hardware security primitives: root of trust, secure boot, TEEs (e.g., TrustZone or equivalent), key management, secure debug, and hardware/software cryptographic implementations. Strong command of applied cryptography and of physical and side-channel attack classes (fault injection, power/EM analysis) and their countermeasures. Hands-on experience with SoC development flows and the interfaces between RTL/silicon design, firmware, and low-level platform software; ability to specify and review security-relevant hardware and firmware. Proven ability to lead threat modeling and to drive security requirements across multi-disciplinary teams from architecture through production. Master’s degree in Electrical/Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Excellent written and verbal communication skills, with a track record of influencing technical direction and mentoring engineers., Experience securing AI/ML accelerators or NPUs, including protection of on-device models and inference pipelines. Familiarity with robotics, autonomous systems, automotive, or other safety-critical domains, and with functional-safety standards (e.g., ISO 26262) alongside security standards (e.g., ISO/SAE 21434, Common Criteria, FIPS 140-3, or PSA Certified). Experience with post-quantum cryptography, confidential computing, or hardware supply-chain security. Prior experience at an early-stage or high-growth semiconductor or hardware company, building security functions and practices from the ground up. Ph.D in Electrical/Computer Engineering, Computer Science, or a related field

About the company

$200,000 - $300,000 a year Compensation & Benefits At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a base salary and very competitive equity compensation, allowing team members to share in the company’s long-term success. The base pay listed represents a good faith estimate that the Company reasonably expects to pay for this position at the time of hire. Actual compensation will depend on multiple factors, including the candidate’s skills, qualifications, relevant experience, and geographic location. In addition to base salary and equity compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team. Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure

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