Senior AI SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS

AWS”s Trainium and Inferentia chips power the world”s largest machine learning clusters. Our team builds C++ models of these custom SoCs that RTL designers, verification engineers, and software teams depend on throughout the silicon development lifecycle. We”re looking for a modeling engineer to build and own models that directly impact how our chips are designed, verified, and brought to production.

What you”ll do:

• Develop and maintain high-fidelity functional model of AI/ML accelerator and its SoC subsystems, including compute engines, memory hierarchies, on-chip interconnects, and data paths - translating architecture specs and RTL behavior into accurate, testable C++ models
• Validate model behavior against RTL simulations, emulation platforms, or silicon measurements; debug discrepancies and drive model-to-RTL correlation to high fidelity
• Partner with design verification teams to integrate models into pre-silicon validation environments and catch architectural bugs early in the design cycle
• Collaborate with architects/micro-architects, RTL design engineers, ML SW engineers, and compiler engineers to evaluate architecture and microarchitecture tradeoffs and help make hardware design decisions
• Contribute to cycle-approximate performance model effort enabling architectural exploration ahead of RTL availability, early software development
• Quantify system-level tradeoffs across compute, memory bandwidth, networking, and storage to influence reference architectures and long-term silicon strategy
• Build and improve modeling infrastructure: simulation frameworks, regression suites, automated correlation checks, and coverage-driven validation flows
• Develop modeling methodologies and tools that scale across multiple IP blocks and SoC generations, improving team efficiency and model reuse

Why this role is interesting:

• Your models are used to verify silicon before it”s built - bugs you catch save months of schedule and millions of dollars
• You”ll work at the intersection of software engineering and chip design, with deep visibility into how custom ML accelerators are architected
• As the team scales, there”s a clear path into architectural modeling - using your models to influence chip design decisions, not just validate them
• Small team, high ownership, direct impact on AWS”s most strategic silicon programs

Machine Learning, Artificial Intelligence (AI), Amazon Web Services (AWS), System-on-a-Chip (SoC), C++ Programming Language, Machine Learning, Verification Engineering, RTL Design, Product Lifecycle, Amazon Web Services (AWS), * Have built functional or performance models of SoCs, ASICs, GPUs, CPUs, or IP blocks

• Are comfortable working with architectural / design specifications or reference implementations and translating them into C++ or SystemC models
• Understand verification concepts and have worked with DV teams or in pre-silicon validation environments
• Care about model fidelity and have experience correlating models against RTL or silicon
• Are interested in expanding into architectural performance modeling as the team grows
• Enjoy working on a small, high-impact team where you own significant pieces of the stack

No ML background needed. You”ll learn the ML accelerator domain on the job.