Senior RTL Design Engineer (Silicon Engineering)

job summary: Join an industry-leading Silicon Engineering team focused on building high-performance digital subsystems and cutting-edge hardware architectures. In this role, you will take ownership of complex digital blocks, defining micro-architecture and driving design implementation through final sign-off.

location: Telecommute job type: Contract salary: $63.33 - 73.33 per hour work hours: 8am to 4pm education: Bachelors

responsibilities:

• Lead micro-architecture definition and detailed RTL design for complex digital hardware blocks.
• Integrate internal and third-party IP into digital subsystems while ensuring seamless control logic.
• Perform design sign-off checks, including Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and synthesis preparation.
• Partner with Digital Verification (DV) teams to assist in debugging and ensure complete code coverage.

qualifications: REQUIRED QUALIFICATIONS

Master’s Degree (MS) in Electrical Engineering, Computer Science, or a related field.

8+ years of expert experience in SystemVerilog/Verilog RTL design and hardware micro-architecture.

Demonstrated expertise in memory controllers, digital block integration, and design sign-off flows (CDC/RDC).

PREFERRED QUALIFICATIONS

Previous exposure to Die-to-Die (D2D) logic or complex subsystem-level design.

Prior experience collaborating directly with hyper-scaler silicon engineering teams.

Strong communication skills and the ability to work independently in a fast-paced environment.

skills: linting,micro-architecture,Interconnect,debug issues,Subsystems,Subsystem,SystemVerilog,Verilog,minimal supervision,Collaboration,architecture,IP integration,technical design,functional specifications,functional coverage

Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

At Randstad Digital, we welcome people of all abilities and want to ensure that our hiring and interview process meets the needs of all applicants. If you require a reasonable accommodation to make your application or interview experience a great one, please contact HRsupport@randstadusa.com.

Pay offered to a successful candidate will be based on several factors including the candidate’s education, work experience, work location, specific job duties, certifications, etc. In addition, Randstad Digital offers a comprehensive benefits package, including: medical, prescription, dental, vision, AD&D, and life insurance offerings, short-term disability, and a 401K plan (all benefits are based on eligibility).

This posting is open for thirty (30) days.

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance.

Qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act.

We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles’ Fair Chance Initiative for Hiring Ordinance.

,

• Lead micro-architecture definition and detailed RTL design for complex digital hardware blocks.
• Integrate internal and third-party IP into digital subsystems while ensuring seamless control logic.
• Perform design sign-off checks, including Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and synthesis preparation.
• Partner with Digital Verification (DV) teams to assist in debugging and ensure complete code coverage.

linting,micro-architecture,Interconnect,debug issues,Subsystems,Subsystem,SystemVerilog,Verilog,minimal supervision,Collaboration,architecture,IP integration,technical design,functional specifications,functional coverage