Role details

Contract type

Permanent contract

Employment type

Full-time (> 32 hours)

Experience level

Expert

Experience required

8 years minimum

Working hours

Regular working hours

Job source

www.juju.com

Tech stack

Microarchitecture Software Debugging Dynamic Random-Access Memory Formal Verification SystemVerilog

Job description

• Architect and implement memory controllers for HBM2E/3, LPDDR5/6, and DDR5.
• Deliver RTL from spec to tape-out: coding, simulation, synthesis, optimization.
• Integrate memory PHY, interposer, and DRAM interfaces into SoC.
• Collaborate with architecture, verification, and PD teams to close timing and power.
• Debug across pre- and post-silicon phases; ensure first-pass success.
• Contribute to other subsystems as gaps arise.

Requirements

• BS/MS in EE/CE, 8+ years of RTL design in advanced SoCs.
• Strong SystemVerilog coding and micro-architecture skills.
• Proven experience with HBM (2/3), LPDDR (5/6), DDR (4/5).
• Solid grasp of timing closure, CDC, power optimization.
• Familiar with synthesis, lint, and UVM/verification methodologies.

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