FPGA Engineer

• Design, develop, and verify RTL logic using Verilog HDL and VHDL.
• Develop, implement, and debug FPGA designs.
• Perform Clock Domain Crossing (CDC) analysis and implement synchronization techniques.
• Design and optimize reset logic, pipelining, FIFOs, and memory interfaces.
• Define and analyze timing constraints and perform Static Timing Analysis (STA).
• Support timing closure and resolve timing-related issues.
• Work with FPGA development and simulation tools such as Vivado, Quartus, Libero, Questa, and ModelSim.
• Perform FPGA hardware bring-up, board-level debugging, and functional validation.
• Analyze clock architecture and interface protocols to ensure reliable system operation.
• Troubleshoot hardware and synchronization issues and collaborate with cross-functional engineering teams.

We are looking for experienced FPGA Engineers with strong expertise in Verilog HDL, VHDL, RTL design, FPGA development, and hardware debugging. The ideal candidates will have hands-on experience in Clock Domain Crossing (CDC), timing analysis, timing closure, and FPGA hardware bring-up.

Candidates should be proficient in FPGA development tools such as Vivado, Quartus, or Libero and have a solid understanding of clock architecture, reset design, synchronization, pipelining, and interface protocols., * 5-7 years of hands-on FPGA engineering experience.

• Strong proficiency in Verilog HDL and RTL design; VHDL experience is also required.
• Experience in FPGA design, implementation, debugging, and hardware bring-up.
• Strong understanding of Clock Domain Crossing (CDC), synchronization, and reset design.
• Experience with Static Timing Analysis (STA), timing constraints, and timing closure.
• Knowledge of clock architecture, pipelining, FIFO design, and memory interfaces.
• Experience with FPGA development and simulation tools.

Preferred Qualifications

• Hands-on experience with Xilinx Vivado, Intel Quartus, or Microchip Libero.
• Experience using Questa or ModelSim for simulation and verification.
• FPGA board-level debugging and hardware validation experience.
• Ability to troubleshoot timing violations and synchronization issues.
• Experience working across multiple FPGA design platforms.