Field-Programmable Gate Arrays Engineer

Intellectt Inc. is seeking experienced FPGA Engineers for a contract opportunity with Eaton in Raleigh, North Carolina. We are looking for candidates with 5-7 years of hands-on experience in FPGA design, Verilog/VHDL RTL development, hardware debugging, and FPGA implementation., * Design, develop, and maintain FPGA logic using Verilog HDL and VHDL.

• Develop and implement RTL designs for FPGA-based hardware systems.
• Perform FPGA synthesis, implementation, simulation, verification, and debugging.
• Analyze and resolve Clock Domain Crossing (CDC), synchronization, and reset-related issues.
• Design and optimize pipelining structures, FIFOs, memory interfaces, and related logic.
• Develop and maintain timing constraints and perform Static Timing Analysis (STA).
• Analyze timing reports, resolve timing violations, and support timing closure.
• Understand and implement appropriate clock architectures for FPGA designs.
• Work with interface protocols and ensure reliable communication between hardware components.
• Use FPGA development tools such as Vivado, Quartus, or Libero for design implementation and analysis.
• Perform RTL simulation and functional verification using Questa, ModelSim, or equivalent tools.
• Support FPGA hardware bring-up, board-level testing, and Real Time debugging.
• Troubleshoot FPGA design issues involving timing, synchronization, logic functionality, and hardware integration.
• Collaborate with hardware, Embedded systems, and cross-functional engineering teams to resolve design issues.
• Document design decisions, verification results, debugging findings, and implementation changes., Interested candidates should submit an updated resume highlighting their FPGA engineering experience, Verilog/VHDL RTL design, FPGA implementation, CDC, STA, timing closure, and hardware debugging expertise.

Please include details of FPGA tools used, hardware bring-up projects, simulation and verification experience, and hands-on work with synchronization, reset design, pipelining, FIFO, and memory interfaces.

The ideal candidates will have strong knowledge of Clock Domain Crossing (CDC), synchronization, reset design, Static Timing Analysis (STA), timing constraints, and timing closure. Experience with FPGA development tools such as Xilinx Vivado, Intel Quartus, Microchip Libero, and simulation tools such as Questa or ModelSim is highly desirable., * 5-7 years of relevant FPGA engineering and design experience.

• Strong hands-on experience with Verilog HDL and RTL design.
• Working knowledge of VHDL and digital logic design.
• Experience with FPGA design implementation, verification, and debugging.
• Understanding of Clock Domain Crossing (CDC), synchronization techniques, and reset design.
• Experience with Static Timing Analysis (STA), timing constraints, and timing closure.
• Knowledge of clock architecture, pipelining, FIFO design, and memory interfaces.
• Hands-on experience with FPGA hardware bring-up and debugging.
• Ability to troubleshoot hardware and RTL design issues systematically.
• Strong analytical, problem-solving, and technical documentation skills.
• A degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field is preferred., * Experience with Xilinx Vivado, Intel Quartus, or Microchip Libero.
• Familiarity with Questa or ModelSim simulation and verification tools.
• Experience resolving CDC, timing, synchronization, and reset-related issues in complex FPGA designs.
• Experience with FPGA board-level debugging and hardware validation.
• Knowledge of digital interface protocols and hardware communication interfaces.
• Experience working in semiconductor, Embedded systems, electronics, or hardware engineering environments.
• Familiarity with multiple FPGA development and simulation toolchains., * The role requires hands-on FPGA design, RTL development, verification, and hardware debugging.
• Candidates should have practical experience with FPGA implementation tools, timing analysis, and hardware bring-up.
• Candidates must have 5-7 years of relevant FPGA engineering experience.
• Candidates must be legally authorized to work in the United States in accordance with applicable laws and the engagement requirements.

Contract: No employer-provided benefits.