Expert Logic Design Engineer

Ciklumis looking for anExpert Logic Design Engineerto join our team in Spain.We are a custom product engineering company that supports both multinational organizations and scaling startups to solve their most complex business challenges. With a global team of over 4,000 highly skilled developers, consultants, analysts and product owners, we engineer technology that redefines industries and shapes the way people live.About the role:We are looking for anExpert Logic Design Engineer to take a leading technical role in the architecture, design, and optimization of next-generation FPGA and ASIC-based control platforms.This position involves solving challenging digital design problems with extremely demanding timing, latency, and performance requirements. You will work closely with system architects, verification engineers, software developers, and hardware specialists, driving technical decisions and contributing to the development of proprietary digital IP.Our client is an innovative technology company developing advanced control and measurement systems for quantum computing. Its hardware and software platforms enable precise, real-time control of complex quantum systems, supporting the evolution of quantum computing from individual qubits to large-scale architectures.Responsibilities:Lead the architecture, microarchitecture, and RTL implementation of complex, high-performance FPGA/ASIC digital subsystemsDesign and optimize highly configurable, ultra-low-latency digital logic using SystemVerilogDrive end-to-end digital IP development, from system requirements and architectural trade-offs to RTL implementation and integrationMake architectural decisions to optimize timing performance, latency, resource utilization, scalability, and power efficiencyAddress complex timing closure, clock-domain crossing, synchronization, and critical-path optimization challengesDevelop advanced digital processing and control architectures, including signal processing pipelines, waveform generation, and deterministic real-time controlDefine hardware-software interfaces and collaborate with software and system architecture teams to ensure efficient system integrationWork closely with verification engineers to define verification strategies and ensure robust functional coverageReview RTL designs, identify architectural and implementation risks, and provide technical guidance to other engineersContribute to the evolution of FPGA-based platforms and the development of reusable digital IP for future ASIC implementationsDrive engineering best practices, design quality, and technical improvements across the development lifecycleRequirements:Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience6+ years of professional experience in complex FPGA or ASIC digital logic designExpert-level proficiency in SystemVerilog RTL design (mandatory)Extensive experience defining digital architectures and microarchitectures for complex hardware systemsProven track record of independently delivering complex digital IP or subsystems from specification to implementationDeep understanding of RTL optimization, logic synthesis, static timing analysis (STA), and timing closureStrong experience optimizing digital designs for deterministic latency, high clock frequencies, resource utilization, and power efficiencyAdvanced knowledge of synchronous digital design, CDC, clocking architectures, and hardware interfacesStrong understanding of FPGA and/or ASIC development methodologies and implementation constraintsExperience with simulation-based verification and debugging of complex digital systemsAbility to evaluate architectural trade-offs, resolve challenging technical issues, and guide implementation decisionsStrong technical leadership, analytical, and communication skillsEnglish proficiency sufficient for effective collaboration within an international engineering teamExtensive experience with AMD/Xilinx FPGA architectures, particularly AMDVersalAdvanced experience with AMDVivado, FPGA implementation, and timing closureFamiliarity with Synopsys VCS, Siemens Questa, and related verification/debugging toolsExperience with ASIC digital IP development and FPGA-to-ASIC design considerationsExperience designing complex DSP pipelines, waveform generation engines, or real-time control architecturesDeep understanding of deterministic, nanosecond-scale timing and synchronizationExperience with high-speed interfaces such as AXI, PCIe, DDR, or proprietary interconnectsExperience with performance, area, and power (PPA) optimizationKnowledge of Python, Tcl, or other languages used for EDA workflow automationExperience leading technical design reviews or mentoring senior engineersBackground in quantum computing, semiconductor development, telecommunications, high-performance instrumentation, or similar advanced technology domainsWhat’s in it for you?Care: your mental and physical health is our priority. We ensure comprehensive company-paid medical insurance and 4 additional undocumented sick leave daysTailored education path: boost your skills and knowledge with our regular internal events (meetups, conferences, workshops), Udemy license, language courses and company-paid certificationsGrowth environment: share your experience and level up your expertise with a community of skilled professionals, locally and globallyFlexibility: Own your schedule - you are the one to decide when to start your working day. Just don’t miss your regular team stand-up. We are there to support your work-life balance and provide 23 vacation days.Opportunities: we value our specialists and always find the best options for them. Our Internal Mobility Program helps change a project if needed to help you grow, excel professionally and fulfill your potentialGlobal impact: work on large-scale projects that redefine industries with international and fast-growing clientsWelcoming environment: feel empowered with a friendly team, open-door policy, informal atmosphere within the company and regular team-building eventsAbout us:At Ciklum, we are always exploring innovations, empowering each other to achieve more, and engineering solutions that matter. With us, you’ll work with cutting-edge technologies, contribute to impactful projects, and be part of a One Team culture that values collaboration and progress.Based in Málaga, our team thrives in one of Andalusia’s leading tech hubs. Enjoy a hybrid work setup, the sunny Mediterranean vibe, and endless opportunities to grow your skills on global-scale projects.Explore, empower, engineer with Ciklum!#J-*****-Ljbffr

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience 6+ years of professional experience in complex FPGA or ASIC digital logic design Expert-level proficiency in SystemVerilog RTL design (mandatory) Extensive experience defining digital architectures and microarchitectures for complex hardware systems Proven track record of independently delivering complex digital IP or subsystems from specification to implementation Deep understanding of RTL optimization, logic synthesis, static timing analysis (STA), and timing closure Strong experience optimizing digital designs for deterministic latency, high clock frequencies, resource utilization, and power efficiency Advanced knowledge of synchronous digital design, CDC, clocking architectures, and hardware interfaces Strong understanding of FPGA and/or ASIC development methodologies and implementation constraints Experience with simulation-based verification and debugging of complex digital systems Ability to evaluate architectural trade-offs, resolve challenging technical issues, and guide implementation decisions Strong technical leadership, analytical, and communication skills English proficiency sufficient for effective collaboration within an international engineering team Extensive experience with AMD/Xilinx FPGA architectures, particularly AMDVersal Advanced experience with AMDVivado, FPGA implementation, and timing closure Familiarity with Synopsys VCS, Siemens Questa, and related verification/debugging tools Experience with ASIC digital IP development and FPGA-to-ASIC design considerations Experience designing complex DSP pipelines, waveform generation engines, or real-time control architectures Deep understanding of deterministic, nanosecond-scale timing and synchronization Experience with high-speed interfaces such as AXI, PCIe, DDR, or proprietary interconnects Experience with performance, area, and power (PPA) optimization Knowledge of Python, Tcl, or other languages used for EDA workflow automation Experience leading technical design reviews or mentoring senior engineers Background in quantum computing, semiconductor development, telecommunications, high-performance instrumentation, or similar advanced technology domains

At Ciklum, we are always exploring innovations, empowering each other to achieve more, and engineering solutions that matter. With us, you’ll work with cutting-edge technologies, contribute to impactful projects, and be part of a One Team culture that values collaboration and progress. Based in Málaga, our team thrives in one of Andalusia’s leading tech hubs. Enjoy a hybrid work setup, the sunny Mediterranean vibe, and endless opportunities to grow your skills on global-scale projects. Explore, empower, engineer with Ciklum! #J-*****-Ljbffr