ASIC / VLSI Engineers

• 8+ years of pre-silicon ASIC / VLSI experience
• Strong background in RTL-based design environments
• Experience at the SoC / full-chip level (not IP-only)
• Solid understanding of ASIC lifecycle (design * tapeout)
• Scripting experience (Python, Tcl, Perl, etc.)
• Strong digital logic fundamentals

Must have:

• Pre-silicon experience only (no post-silicon / firmware-only backgrounds), * RTL design + microarchitecture
• Ethernet (802.3), MAC / PCS / SerDes / PHY
• High-speed designs (100G+ preferred)
• Tapeout + productization experience

STA Engineer

• SoC-level timing analysis & closure
• PrimeTime, Tempus, or similar

Physical Design Engineer

• Floorplanning, CTS, routing, signoff
• Timing, congestion, power optimization

Design Verification Engineer

• SoC-level verification (required)
• SystemVerilog / UVM
• Full verification lifecycle

What Sets You Apart

• Experience with complex SoC / full-chip tapeouts
• Ability to work cross-functionally (RTL, DV, PD)
• Background in advanced nodes (28nm and below preferred)

We are hiring 4 experienced ASIC / VLSI Engineers (8+ years) for permanent, full-time, onsite roles in Silicon Valley supporting advanced semiconductor and AI / networking programs. These roles are within a leading semiconductor design services organization, supporting long-term engagements with tier-1 clients in networking and advanced silicon.