Senior Digital Design Engineer

Job Title: Senior Digital Design Engineer Location: Cambridge, United Kingdom Job Type: Permanent Salary: 65K - 88K GBP per annum DOE Role Overview: Work at the forefront of open silicon and hardware security, contributing to next-generation secure ASIC/SoC designs based around RISC-V, cryptographic accelerators and hardware security IP. This is a hands-on opportunity to make a direct impact on advanced silicon architecture and RTL design. Key Responsibilities: Contribute to the architecture and specification of new digital designs and enhancements to existing IP. Develop and maintain System Verilog RTL across a range of digital silicon IP. Work closely with Design Verification engineers on test plans, coverage and regression debugging. Collaborate with security specialists to implement robust hardware security and protection features. Support verification closure through both design expertise and hands-on verification contributions. Participate in code reviews and collaborative

development within an open-source engineering environment. Work with engineers across multiple organisations and disciplines to support IP integration into silicon products. Take technical ownership of IPs or subsystems where required, ensuring high-quality and timely delivery. Provide technical guidance and mentoring to less experienced engineers. Experience Required: Minimum 4+ yrs’ industry experience in digital IC/ASIC design Master’s degree or PhD in Electrical/Electronic Engineering or another relevant technical discipline. Strong hands-on System Verilog / RTL experience. Good knowledge of industry-standard EDA tools from Synopsys, Cadence and/or Siemens. Experience working with Git-based development and code collaboration platforms such as GitHub, GitLab or Gerrit. Proven experience contributing to full-chip development cycles, from initial planning and RTL through tape-out, bring-up and post-silicon validation. Ability to take ownership of significant areas of design and work with minimal supervision. Comfortable contributing beyond RTL where required, including silicon architecture, system integration, verification, chip bring-up and post-silicon testing. Strong project ownership skills, including estimating work, communicating progress and delivering to agreed timelines. Desirable: Experience across multiple areas of digital silicon/IP, such as CPU cores, memory subsystems, interconnects, I/O controllers or cryptographic accelerators. Understanding of hardware security, including countermeasures against physical attacks such as side-channel analysis and fault injection. Experience with RISC-V or similar processor architectures. Programming experience in Python, C and/or Rust, particularly for automation, RTL generation, software interfaces, testing or system integration. TPBN1_UKTJ