Principal Front-End Design Engineer

Synopsys
Sunnyvale, CA, United States
14 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
10 years minimum
Compensation
$191,000.0 - $286,000.0
Working hours
Regular working hours
Job source

Tech stack

Artificial Intelligence Systems Engineering Computer Engineering Software Debugging Python (Programming Language) SystemVerilog Tcl (Programming Language) Application Specific Integrated Circuits Front End Software Development

Job description

Synopsys is a leader in silicon-to-systems engineering solutions, helping customers accelerate innovation in AI-driven products through industry-leading EDA, IP, and design solutions. You Are As a Principal Front-End Design Engineer, you will lead methodology, subsystem architecture, and AI-enabled design innovation across IP and SoC development. You will build scalable design solutions, improve engineering productivity, and drive best practices across global teams. What You’ll Be Doing

  • Develop and deploy AI-driven solutions for verification, synthesis, constraints, and DFT workflows.
  • Architect reusable subsystem reference designs for Synopsys IP.
  • Debug and optimize front-end design methodologies and automation flows.
  • Drive adoption of best practices across design and verification teams.
  • Collaborate with EDA, IP, and customer-facing engineers to solve complex design challenges.
  • Mentor engineers through technical leadership and knowledge sharing.

Requirements

  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of ASIC, SoC, or IP design and verification experience.
  • Expertise in verification, synthesis, timing constraints, DFT, CDC/RDC, or lint methodologies.
  • Strong experience with Synopsys tools such as VCS, VC SpyGlass, Fusion Compiler, Design Compiler, and TestMAX.
  • Proficient in SystemVerilog, UVM, Tcl, Python, or similar languages.
  • Demonstrated technical leadership and influence across cross-functional engineering teams.

What Sets You Apart

  • Deep understanding of IP reuse, subsystem integration, and SoC development. Passion for
  • ing AI to improve design productivity and quality.
  • Strong problem-solving, communication, and mentoring skills.
  • Ability to translate complex technical challenges into scalable, practical solutions.

Benefits & conditions

You will be a member of the Digital Methodology Interop Engineering team, a team of engineers dedicated to advancing IP and subsystem design excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. You will help shape the future of SoC design with Synopsys IP. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can

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