STA Engineer

We are looking for experienced STA Engineers responsible for timing analysis, timing closure, and sign-off of complex ASIC/SoC designs. The ideal candidate will have strong hands-on experience in Static Timing Analysis, timing constraints, MCMM analysis, and timing closure, along with a solid understanding of synthesis and physical-design flows. Key Responsibilities

• Perform Static Timing Analysis (STA) for complex designs.
• Analyze setup, hold, recovery, and removal violations.
• Develop and validate timing constraints.
• Perform MCMM timing analysis.
• Debug timing violations and drive timing closure.
• Analyze clock definitions, generated clocks, and timing exceptions.
• Work closely with RTL, synthesis, and physical design teams.
• Support ECO implementation and timing optimization.
• Generate and analyze timing reports.

• Strong STA and timing-closure experience.
• Hands-on experience with Synopsys PrimeTime or equivalent.
• Strong knowledge of SDC.
• Strong understanding of setup/hold analysis.
• Experience with MCMM.
• Strong knowledge of timing constraints.
• Tcl scripting experience.
• Understanding of synthesis and physical-design flows.

Jones Lang LaSalle

• Sunnyvale, CA
• $203,673-203,674 per year JLL empowers you to shape a brighter way. Our people at JLL are shaping the future of real estate for a better world by combining world class services, advisory and technology fo…