Sr DFT Engineer (100% Remote)

We are seeking an experienced Senior DFT Engineer to lead test architecture and implementation for complex SoCs. You will work closely with design and verification teams to drive DFT requirements from RTL through to silicon bring-up, ensuring the highest quality test coverage., * Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for next-generation ASIC/SoC designs.

• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and rigorous fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

• Experience: 8+ years of proven industry experience in ASIC DFT engineering.
• IJTAG: Strong hands-on expertise with IEEE 1687 (IJTAG) architecture, specifically utilizing ICL and PDL formats.
• DFT Tools: Deep proficiency with the Mentor Graphics (Siemens) Tessent tool suite.
• Simulation: Solid simulation, verification, and debug skills using Xcelium, VCS, or QuestaSim.
• Core Skills: Fluency in Verilog/SystemVerilog and strong scripting abilities (Tcl, Python, or Perl).

Education: BS or MS in Electrical Engineering, Computer Engineering, or a related field.

The anticipated annual base salary for this position is between $135,000 to $150,000, which also includes a comprehensive benefits package.

Full-Time Benefits: 15 days of PTO per calendar year 10 paid Holidays per calendar year Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents Dental & Vision: Company covers 50% of premiums for Employee and Dependents Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance Employee Assistant Program (EAP) 401k - Traditional & Roth Life/AD&D and Long-Term Disability Tuition reimbursement